Gecko [ tsuru-no-tsurugi.tokyo ]

Name	Size	Permission	Date
amba	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
atomic	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
avf	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
bcma	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
byteorder	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
can	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
ceph	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
clk	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
crush	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
decompress	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
device	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
dma	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
dsa	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
extcon	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
firmware	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
fpga	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
fsl	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
gpio	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
greybus	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
hsi	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
i3c	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
iio	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
input	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
irqchip	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
isdn	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
lockd	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mailbox	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mdio	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mfd	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mlx4	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mlx5	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mmc	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mtd	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
mux	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
net	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
netfilter	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
netfilter_arp	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
netfilter_bridge	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
netfilter_ipv4	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
netfilter_ipv6	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
pcs	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
perf	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
phy	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
pinctrl	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
platform_data	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
power	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
qed	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
raid	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
regulator	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
remoteproc	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
reset	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
rpmsg	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
rtc	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
sched	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
soc	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
soundwire	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
spi	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
ssb	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
sunrpc	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
surface_aggregator	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
ulpi	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
unaligned	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
usb	[ DIR ]	drwxr-xr-x	2026-06-27 06:50
8250_pci.h	1.01 KB	-rw-r--r--	2021-11-01 05:53
a.out.h	354 B	-rw-r--r--	2021-11-01 05:53
acct.h	2.49 KB	-rw-r--r--	2021-11-01 05:53
acpi.h	39.94 KB	-rw-r--r--	2026-06-20 00:54
acpi_dma.h	3.08 KB	-rw-r--r--	2021-11-01 05:53
acpi_iort.h	2.35 KB	-rw-r--r--	2026-06-20 00:54
acpi_mdio.h	819 B	-rw-r--r--	2026-06-20 00:54
acpi_pmtmr.h	674 B	-rw-r--r--	2021-11-01 05:53
acpi_viot.h	478 B	-rw-r--r--	2026-06-20 00:54
adb.h	1.79 KB	-rw-r--r--	2021-11-01 05:53
adfs_fs.h	574 B	-rw-r--r--	2021-11-01 05:53
adreno-smmu-priv.h	2.74 KB	-rw-r--r--	2021-11-01 05:53
adxl.h	310 B	-rw-r--r--	2021-11-01 05:53
aer.h	1.78 KB	-rw-r--r--	2021-11-01 05:53
agp_backend.h	3.45 KB	-rw-r--r--	2021-11-01 05:53
agpgart.h	3.79 KB	-rw-r--r--	2021-11-01 05:53
ahci-remap.h	607 B	-rw-r--r--	2021-11-01 05:53
ahci_platform.h	1.71 KB	-rw-r--r--	2026-06-20 00:54
aio.h	651 B	-rw-r--r--	2021-11-01 05:53
alarmtimer.h	1.94 KB	-rw-r--r--	2021-11-01 05:53
alcor_pci.h	8.83 KB	-rw-r--r--	2021-11-01 05:53
align.h	552 B	-rw-r--r--	2021-11-01 05:53
altera_jtaguart.h	379 B	-rw-r--r--	2021-11-01 05:53
altera_uart.h	397 B	-rw-r--r--	2021-11-01 05:53
amd-iommu.h	6.18 KB	-rw-r--r--	2021-11-01 05:53
anon_inodes.h	670 B	-rw-r--r--	2021-11-01 05:53
apm-emulation.h	1.56 KB	-rw-r--r--	2021-11-01 05:53
apm_bios.h	2.25 KB	-rw-r--r--	2021-11-01 05:53
apple-gmux.h	918 B	-rw-r--r--	2021-11-01 05:53
apple_bl.h	498 B	-rw-r--r--	2021-11-01 05:53
arch_topology.h	2.49 KB	-rw-r--r--	2021-11-01 05:53
arm-cci.h	1.36 KB	-rw-r--r--	2021-11-01 05:53
arm-smccc.h	16.97 KB	-rw-r--r--	2026-06-20 00:54
arm_ffa.h	7.37 KB	-rw-r--r--	2026-06-20 00:54
arm_sdei.h	2.67 KB	-rw-r--r--	2026-06-20 00:54
armada-37xx-rwtm-mailbox.h	431 B	-rw-r--r--	2021-11-01 05:53
array_size.h	332 B	-rw-r--r--	2026-06-20 00:54
ascii85.h	555 B	-rw-r--r--	2021-11-01 05:53
asn1.h	1.79 KB	-rw-r--r--	2021-11-01 05:53
asn1_ber_bytecode.h	2.52 KB	-rw-r--r--	2021-11-01 05:53
asn1_decoder.h	468 B	-rw-r--r--	2021-11-01 05:53
asn1_encoder.h	1006 B	-rw-r--r--	2021-11-01 05:53
assoc_array.h	2.88 KB	-rw-r--r--	2021-11-01 05:53
assoc_array_priv.h	5.3 KB	-rw-r--r--	2021-11-01 05:53
async.h	4.33 KB	-rw-r--r--	2026-06-20 00:54
async_tx.h	6.7 KB	-rw-r--r--	2021-11-01 05:53
ata.h	33.01 KB	-rw-r--r--	2026-06-20 00:54
ata_platform.h	749 B	-rw-r--r--	2021-11-01 05:53
atalk.h	4.48 KB	-rw-r--r--	2021-11-01 05:53
ath9k_platform.h	1.44 KB	-rw-r--r--	2021-11-01 05:53
atm.h	287 B	-rw-r--r--	2021-11-01 05:53
atm_tcp.h	511 B	-rw-r--r--	2021-11-01 05:53
atmdev.h	10.23 KB	-rw-r--r--	2026-06-20 00:54
atmel-isc-media.h	2.07 KB	-rw-r--r--	2021-11-01 05:53
atmel-mci.h	1.4 KB	-rw-r--r--	2021-11-01 05:53
atmel-ssc.h	9.74 KB	-rw-r--r--	2021-11-01 05:53
atmel_pdc.h	1.26 KB	-rw-r--r--	2021-11-01 05:53
atomic.h	2.58 KB	-rw-r--r--	2021-11-01 05:53
attribute_container.h	2.74 KB	-rw-r--r--	2021-11-01 05:53
audit.h	19.45 KB	-rw-r--r--	2026-06-20 00:54
auto_dev-ioctl.h	296 B	-rw-r--r--	2021-11-01 05:53
auto_fs.h	278 B	-rw-r--r--	2021-11-01 05:53
auxiliary_bus.h	2.48 KB	-rw-r--r--	2021-11-01 05:53
auxvec.h	304 B	-rw-r--r--	2021-11-01 05:53
average.h	2.42 KB	-rw-r--r--	2021-11-01 05:53
backing-dev-defs.h	8.55 KB	-rw-r--r--	2021-11-01 05:53
backing-dev.h	11.9 KB	-rw-r--r--	2026-06-20 00:54
backlight.h	13.13 KB	-rw-r--r--	2021-11-01 05:53
badblocks.h	2.14 KB	-rw-r--r--	2021-11-01 05:53
balloon_compaction.h	5.75 KB	-rw-r--r--	2026-06-20 00:54
bcd.h	559 B	-rw-r--r--	2021-11-01 05:53
bch.h	2.1 KB	-rw-r--r--	2021-11-01 05:53
bcm47xx_nvram.h	1.01 KB	-rw-r--r--	2021-11-01 05:53
bcm47xx_sprom.h	616 B	-rw-r--r--	2021-11-01 05:53
bcm47xx_wdt.h	555 B	-rw-r--r--	2021-11-01 05:53
bcm963xx_nvram.h	2.96 KB	-rw-r--r--	2021-11-01 05:53
bcm963xx_tag.h	3.6 KB	-rw-r--r--	2021-11-01 05:53
binfmts.h	4.57 KB	-rw-r--r--	2026-06-20 00:54
bio.h	19.64 KB	-rw-r--r--	2021-11-01 05:53
bit_spinlock.h	2.3 KB	-rw-r--r--	2021-11-01 05:53
bitfield.h	5.33 KB	-rw-r--r--	2026-06-20 00:54
bitmap.h	22.13 KB	-rw-r--r--	2026-06-20 00:54
bitops.h	8.53 KB	-rw-r--r--	2021-11-01 05:53
bitrev.h	2.53 KB	-rw-r--r--	2021-11-01 05:53
bits.h	1.35 KB	-rw-r--r--	2021-11-01 05:53
blk-cgroup.h	22.12 KB	-rw-r--r--	2026-06-20 00:54
blk-crypto.h	4.02 KB	-rw-r--r--	2026-06-20 00:54
blk-mq-pci.h	269 B	-rw-r--r--	2021-11-01 05:53
blk-mq-rdma.h	273 B	-rw-r--r--	2021-11-01 05:53
blk-mq-virtio.h	293 B	-rw-r--r--	2021-11-01 05:53
blk-mq.h	19.37 KB	-rw-r--r--	2021-11-01 05:53
blk-pm.h	708 B	-rw-r--r--	2026-06-20 00:54
blk_types.h	15.3 KB	-rw-r--r--	2026-06-20 00:54
blkdev.h	56.68 KB	-rw-r--r--	2026-06-20 00:54
blkpg.h	436 B	-rw-r--r--	2021-11-01 05:53
blktrace_api.h	3.77 KB	-rw-r--r--	2021-11-01 05:53
blockgroup_lock.h	810 B	-rw-r--r--	2021-11-01 05:53
bma150.h	1.26 KB	-rw-r--r--	2021-11-01 05:53
bootconfig.h	8.51 KB	-rw-r--r--	2026-06-20 00:54
bootmem_info.h	1.69 KB	-rw-r--r--	2026-06-20 00:54
bottom_half.h	974 B	-rw-r--r--	2021-11-01 05:53
bpf-cgroup.h	18.36 KB	-rw-r--r--	2026-06-20 00:54
bpf-netns.h	1.52 KB	-rw-r--r--	2021-11-01 05:53
bpf.h	74.43 KB	-rw-r--r--	2026-06-20 00:54
bpf_lirc.h	698 B	-rw-r--r--	2021-11-01 05:53
bpf_local_storage.h	5.23 KB	-rw-r--r--	2021-11-01 05:53
bpf_lsm.h	1.42 KB	-rw-r--r--	2021-11-01 05:53
bpf_trace.h	166 B	-rw-r--r--	2021-11-01 05:53
bpf_types.h	5.41 KB	-rw-r--r--	2021-11-01 05:53
bpf_verifier.h	20.38 KB	-rw-r--r--	2026-06-20 00:54
bpfilter.h	791 B	-rw-r--r--	2021-11-01 05:53
bpfptr.h	1.98 KB	-rw-r--r--	2026-06-20 00:54
brcmphy.h	13.67 KB	-rw-r--r--	2021-11-01 05:53
bsearch.h	624 B	-rw-r--r--	2021-11-01 05:53
bsg-lib.h	1.72 KB	-rw-r--r--	2021-11-01 05:53
bsg.h	492 B	-rw-r--r--	2021-11-01 05:53
btf.h	7.26 KB	-rw-r--r--	2021-11-01 05:53
btf_ids.h	5.33 KB	-rw-r--r--	2026-06-20 00:54
btree-128.h	2.67 KB	-rw-r--r--	2021-11-01 05:53
btree-type.h	3.9 KB	-rw-r--r--	2021-11-01 05:53
btree.h	6.84 KB	-rw-r--r--	2021-11-01 05:53
btrfs.h	145 B	-rw-r--r--	2021-11-01 05:53
buffer_head.h	14.47 KB	-rw-r--r--	2026-06-20 00:54
bug.h	2.17 KB	-rw-r--r--	2021-11-01 05:53
build-salt.h	375 B	-rw-r--r--	2021-11-01 05:53
build_bug.h	2.76 KB	-rw-r--r--	2021-11-01 05:53
buildid.h	561 B	-rw-r--r--	2021-11-01 05:53
bvec.h	6.17 KB	-rw-r--r--	2021-11-01 05:53
c2port.h	1.35 KB	-rw-r--r--	2021-11-01 05:53
cache.h	2.55 KB	-rw-r--r--	2021-11-01 05:53
cacheinfo.h	3.75 KB	-rw-r--r--	2021-11-01 05:53
capability.h	8.29 KB	-rw-r--r--	2021-11-01 05:53
cb710.h	5.36 KB	-rw-r--r--	2021-11-01 05:53
cc_platform.h	2.32 KB	-rw-r--r--	2026-06-20 00:54
cciss_ioctl.h	1.03 KB	-rw-r--r--	2021-11-01 05:53
ccp.h	18.14 KB	-rw-r--r--	2021-11-01 05:53
cdev.h	845 B	-rw-r--r--	2021-11-01 05:53
cdrom.h	8.98 KB	-rw-r--r--	2021-11-01 05:53
cfag12864b.h	1.47 KB	-rw-r--r--	2021-11-01 05:53
cfi.h	1.13 KB	-rw-r--r--	2021-11-01 05:53
cgroup-defs.h	24.23 KB	-rw-r--r--	2026-06-20 00:54
cgroup.h	28.16 KB	-rw-r--r--	2026-06-20 00:54
cgroup_rdma.h	1.18 KB	-rw-r--r--	2021-11-01 05:53
cgroup_subsys.h	1.23 KB	-rw-r--r--	2021-11-01 05:53
circ_buf.h	1.09 KB	-rw-r--r--	2021-11-01 05:53
cleancache.h	3.89 KB	-rw-r--r--	2021-11-01 05:53
cleanup.h	4.87 KB	-rw-r--r--	2026-06-20 00:54
clk-provider.h	57.94 KB	-rw-r--r--	2026-06-20 00:54
clk.h	33.61 KB	-rw-r--r--	2026-06-20 00:54
clkdev.h	1.29 KB	-rw-r--r--	2021-11-01 05:53
clockchips.h	7.27 KB	-rw-r--r--	2021-11-01 05:53
clocksource.h	9.99 KB	-rw-r--r--	2026-06-20 00:54
clocksource_ids.h	247 B	-rw-r--r--	2021-11-01 05:53
cm4000_cs.h	199 B	-rw-r--r--	2021-11-01 05:53
cma.h	1.96 KB	-rw-r--r--	2026-06-20 00:54
cn_proc.h	1.85 KB	-rw-r--r--	2021-11-01 05:53
cnt32_to_63.h	3.46 KB	-rw-r--r--	2021-11-01 05:53
coda.h	2.16 KB	-rw-r--r--	2021-11-01 05:53
compaction.h	7.15 KB	-rw-r--r--	2021-11-01 05:53
compat.h	31.37 KB	-rw-r--r--	2026-06-20 00:54
compiler-clang.h	4.05 KB	-rw-r--r--	2026-06-20 00:54
compiler-gcc.h	4.9 KB	-rw-r--r--	2026-06-20 00:54
compiler-intel.h	949 B	-rw-r--r--	2021-11-01 05:53
compiler-version.h	517 B	-rw-r--r--	2021-11-01 05:53
compiler.h	8.35 KB	-rw-r--r--	2026-06-20 00:54
compiler_attributes.h	13.24 KB	-rw-r--r--	2026-06-20 00:54
compiler_types.h	10.76 KB	-rw-r--r--	2026-06-20 00:54
completion.h	4 KB	-rw-r--r--	2021-11-01 05:53
component.h	4.07 KB	-rw-r--r--	2021-11-01 05:53
configfs.h	8.48 KB	-rw-r--r--	2021-11-01 05:53
connector.h	3.83 KB	-rw-r--r--	2021-11-01 05:53
console.h	7.58 KB	-rw-r--r--	2026-06-20 00:54
console_struct.h	7.08 KB	-rw-r--r--	2026-06-20 00:54
consolemap.h	1.05 KB	-rw-r--r--	2021-11-01 05:53
const.h	421 B	-rw-r--r--	2021-11-01 05:53
container.h	610 B	-rw-r--r--	2021-11-01 05:53
context_tracking.h	3.28 KB	-rw-r--r--	2021-11-01 05:53
context_tracking_state.h	1.58 KB	-rw-r--r--	2021-11-01 05:53
cookie.h	1.22 KB	-rw-r--r--	2021-11-01 05:53
cordic.h	2.08 KB	-rw-r--r--	2021-11-01 05:53
coredump.h	1.13 KB	-rw-r--r--	2026-06-20 00:54
coresight-pmu.h	1.32 KB	-rw-r--r--	2021-11-01 05:53
coresight-stm.h	152 B	-rw-r--r--	2021-11-01 05:53
coresight.h	18.02 KB	-rw-r--r--	2026-06-20 00:54
count_zeros.h	1.42 KB	-rw-r--r--	2021-11-01 05:53
counter.h	14.96 KB	-rw-r--r--	2026-06-20 00:54
cper.h	16.55 KB	-rw-r--r--	2026-06-20 00:54
cpu.h	8.29 KB	-rw-r--r--	2026-06-20 00:54
cpu_cooling.h	1.86 KB	-rw-r--r--	2021-11-01 05:53
cpu_pm.h	2.38 KB	-rw-r--r--	2021-11-01 05:53
cpu_rmap.h	1.68 KB	-rw-r--r--	2021-11-01 05:53
cpufeature.h	1.71 KB	-rw-r--r--	2021-11-01 05:53
cpufreq.h	32.76 KB	-rw-r--r--	2026-06-20 00:54
cpuhotplug.h	16.55 KB	-rw-r--r--	2026-06-20 00:54
cpuidle.h	10.27 KB	-rw-r--r--	2021-11-01 05:53
cpuidle_haltpoll.h	312 B	-rw-r--r--	2021-11-01 05:53
cpumask.h	29.38 KB	-rw-r--r--	2026-06-20 00:54
cpuset.h	8.16 KB	-rw-r--r--	2026-06-20 00:54
crash_core.h	3.38 KB	-rw-r--r--	2021-11-01 05:53
crash_dump.h	4.05 KB	-rw-r--r--	2021-11-01 05:53
crc-ccitt.h	609 B	-rw-r--r--	2021-11-01 05:53
crc-itu-t.h	531 B	-rw-r--r--	2021-11-01 05:53
crc-t10dif.h	453 B	-rw-r--r--	2021-11-01 05:53
crc16.h	540 B	-rw-r--r--	2021-11-01 05:53
crc32.h	2.83 KB	-rw-r--r--	2021-11-01 05:53
crc32c.h	331 B	-rw-r--r--	2021-11-01 05:53
crc32poly.h	610 B	-rw-r--r--	2021-11-01 05:53
crc4.h	192 B	-rw-r--r--	2021-11-01 05:53
crc64.h	280 B	-rw-r--r--	2021-11-01 05:53
crc7.h	316 B	-rw-r--r--	2021-11-01 05:53
crc8.h	3.66 KB	-rw-r--r--	2021-11-01 05:53
cred.h	12.5 KB	-rw-r--r--	2026-06-20 00:54
crypto.h	27.24 KB	-rw-r--r--	2026-06-20 00:54
cs5535.h	6.13 KB	-rw-r--r--	2021-11-01 05:53
ctype.h	1.87 KB	-rw-r--r--	2021-11-01 05:53
cuda.h	613 B	-rw-r--r--	2021-11-01 05:53
damon.h	10.35 KB	-rw-r--r--	2021-11-01 05:53
dasd_mod.h	204 B	-rw-r--r--	2021-11-01 05:53
davinci_emac.h	1.05 KB	-rw-r--r--	2021-11-01 05:53
dax.h	6.56 KB	-rw-r--r--	2021-11-01 05:53
dca.h	1.88 KB	-rw-r--r--	2021-11-01 05:53
dcache.h	18.63 KB	-rw-r--r--	2021-11-01 05:53
dccp.h	10.73 KB	-rw-r--r--	2021-11-01 05:53
debug_locks.h	1.59 KB	-rw-r--r--	2021-11-01 05:53
debugfs.h	11.97 KB	-rw-r--r--	2026-06-20 00:54
debugobjects.h	3.99 KB	-rw-r--r--	2021-11-01 05:53
delay.h	2.43 KB	-rw-r--r--	2026-06-20 00:54
delayacct.h	5.45 KB	-rw-r--r--	2021-11-01 05:53
delayed_call.h	709 B	-rw-r--r--	2021-11-01 05:53
dev_printk.h	9.19 KB	-rw-r--r--	2026-06-20 00:54
devcoredump.h	2.21 KB	-rw-r--r--	2021-11-01 05:53
devfreq-event.h	5.95 KB	-rw-r--r--	2021-11-01 05:53
devfreq.h	14.03 KB	-rw-r--r--	2026-06-20 00:54
devfreq_cooling.h	2.7 KB	-rw-r--r--	2021-11-01 05:53
device-mapper.h	18.92 KB	-rw-r--r--	2021-11-01 05:53
device.h	33.2 KB	-rw-r--r--	2026-06-20 00:54
device_cgroup.h	1.57 KB	-rw-r--r--	2021-11-01 05:53
devm-helpers.h	2.68 KB	-rw-r--r--	2021-11-01 05:53
devpts_fs.h	1.13 KB	-rw-r--r--	2021-11-01 05:53
dfl.h	2.38 KB	-rw-r--r--	2021-11-01 05:53
digsig.h	1.18 KB	-rw-r--r--	2021-11-01 05:53
dim.h	9.2 KB	-rw-r--r--	2026-06-20 00:54
dio.h	10.76 KB	-rw-r--r--	2021-11-01 05:53
dirent.h	215 B	-rw-r--r--	2021-11-01 05:53
dlm.h	5.86 KB	-rw-r--r--	2021-11-01 05:53
dlm_plock.h	532 B	-rw-r--r--	2021-11-01 05:53
dm-bufio.h	4.88 KB	-rw-r--r--	2021-11-01 05:53
dm-dirty-log.h	3.94 KB	-rw-r--r--	2021-11-01 05:53
dm-io.h	1.93 KB	-rw-r--r--	2021-11-01 05:53
dm-kcopyd.h	2.94 KB	-rw-r--r--	2021-11-01 05:53
dm-region-hash.h	3.11 KB	-rw-r--r--	2021-11-01 05:53
dm9000.h	987 B	-rw-r--r--	2021-11-01 05:53
dma-buf-map.h	8.12 KB	-rw-r--r--	2021-11-01 05:53
dma-buf.h	20.47 KB	-rw-r--r--	2026-06-20 00:54
dma-direct.h	3.59 KB	-rw-r--r--	2021-11-01 05:53
dma-direction.h	407 B	-rw-r--r--	2021-11-01 05:53
dma-fence-array.h	2.14 KB	-rw-r--r--	2021-11-01 05:53
dma-fence-chain.h	3.07 KB	-rw-r--r--	2021-11-01 05:53
dma-fence.h	20.86 KB	-rw-r--r--	2026-06-20 00:54
dma-heap.h	1.58 KB	-rw-r--r--	2021-11-01 05:53
dma-iommu.h	2.21 KB	-rw-r--r--	2021-11-01 05:53
dma-map-ops.h	12.89 KB	-rw-r--r--	2026-06-20 00:54
dma-mapping.h	20.11 KB	-rw-r--r--	2026-06-20 00:54
dma-resv.h	11.95 KB	-rw-r--r--	2026-06-20 00:54
dmaengine.h	53.57 KB	-rw-r--r--	2026-06-20 00:54
dmapool.h	1.79 KB	-rw-r--r--	2021-11-01 05:53
dmar.h	7.74 KB	-rw-r--r--	2021-11-01 05:53
dmi.h	4.27 KB	-rw-r--r--	2021-11-01 05:53
dnotify.h	1.02 KB	-rw-r--r--	2026-06-20 00:54
dns_resolver.h	1.36 KB	-rw-r--r--	2021-11-01 05:53
dqblk_qtree.h	2.19 KB	-rw-r--r--	2021-11-01 05:53
dqblk_v1.h	327 B	-rw-r--r--	2021-11-01 05:53
dqblk_v2.h	406 B	-rw-r--r--	2021-11-01 05:53
drbd.h	10.07 KB	-rw-r--r--	2021-11-01 05:53
drbd_genl.h	21.49 KB	-rw-r--r--	2021-11-01 05:53
drbd_genl_api.h	1.77 KB	-rw-r--r--	2021-11-01 05:53
drbd_limits.h	7.82 KB	-rw-r--r--	2021-11-01 05:53
ds2782_battery.h	158 B	-rw-r--r--	2021-11-01 05:53
dtlk.h	3.5 KB	-rw-r--r--	2021-11-01 05:53
dtpm.h	1.64 KB	-rw-r--r--	2021-11-01 05:53
dw_apb_timer.h	1.53 KB	-rw-r--r--	2021-11-01 05:53
dynamic_debug.h	6.32 KB	-rw-r--r--	2026-06-20 00:54
dynamic_queue_limits.h	3.72 KB	-rw-r--r--	2021-11-01 05:53
earlycpio.h	359 B	-rw-r--r--	2021-11-01 05:53
ecryptfs.h	3.82 KB	-rw-r--r--	2021-11-01 05:53
edac.h	19.46 KB	-rw-r--r--	2026-06-20 00:54
edd.h	1.05 KB	-rw-r--r--	2021-11-01 05:53
eeprom_93cx6.h	2.64 KB	-rw-r--r--	2026-06-20 00:54
eeprom_93xx46.h	1.04 KB	-rw-r--r--	2021-11-01 05:53
efi-bgrt.h	644 B	-rw-r--r--	2021-11-01 05:53
efi.h	42.03 KB	-rw-r--r--	2026-06-20 00:54
efi_embedded_fw.h	1.04 KB	-rw-r--r--	2021-11-01 05:53
efs_vh.h	1.55 KB	-rw-r--r--	2021-11-01 05:53
eisa.h	2.96 KB	-rw-r--r--	2021-11-01 05:53
elevator.h	5.52 KB	-rw-r--r--	2021-11-01 05:53
elf-fdpic.h	1.98 KB	-rw-r--r--	2021-11-01 05:53
elf-randomize.h	583 B	-rw-r--r--	2021-11-01 05:53
elf.h	2.96 KB	-rw-r--r--	2021-11-01 05:53
elfcore-compat.h	1.27 KB	-rw-r--r--	2021-11-01 05:53
elfcore.h	4.11 KB	-rw-r--r--	2021-11-01 05:53
elfnote-lto.h	314 B	-rw-r--r--	2021-11-01 05:53
elfnote.h	3.54 KB	-rw-r--r--	2021-11-01 05:53
enclosure.h	4.02 KB	-rw-r--r--	2021-11-01 05:53
energy_model.h	8.17 KB	-rw-r--r--	2021-11-01 05:53
entry-common.h	16.95 KB	-rw-r--r--	2021-11-01 05:53
entry-kvm.h	2.73 KB	-rw-r--r--	2026-06-20 00:54
err.h	1.49 KB	-rw-r--r--	2021-11-01 05:53
errname.h	283 B	-rw-r--r--	2021-11-01 05:53
errno.h	1.45 KB	-rw-r--r--	2021-11-01 05:53
error-injection.h	607 B	-rw-r--r--	2021-11-01 05:53
errqueue.h	524 B	-rw-r--r--	2021-11-01 05:53
errseq.h	382 B	-rw-r--r--	2021-11-01 05:53
etherdevice.h	17.19 KB	-rw-r--r--	2026-06-20 00:54
ethtool.h	31.74 KB	-rw-r--r--	2026-06-20 00:54
ethtool_netlink.h	1.98 KB	-rw-r--r--	2026-06-20 00:54
eventfd.h	2.28 KB	-rw-r--r--	2026-06-20 00:54
eventpoll.h	2.41 KB	-rw-r--r--	2026-06-20 00:54
evm.h	3.42 KB	-rw-r--r--	2021-11-01 05:53
export.h	5.27 KB	-rw-r--r--	2026-06-20 00:54
exportfs.h	8.22 KB	-rw-r--r--	2026-06-20 00:54
ext2_fs.h	967 B	-rw-r--r--	2021-11-01 05:53
extable.h	1.28 KB	-rw-r--r--	2021-11-01 05:53
extcon-provider.h	3.83 KB	-rw-r--r--	2021-11-01 05:53
extcon.h	10.16 KB	-rw-r--r--	2026-06-20 00:54
f2fs_fs.h	19.01 KB	-rw-r--r--	2026-06-20 00:54
f75375s.h	541 B	-rw-r--r--	2021-11-01 05:53
falloc.h	1.59 KB	-rw-r--r--	2021-11-01 05:53
fanotify.h	4.44 KB	-rw-r--r--	2026-06-20 00:54
fault-inject-usercopy.h	496 B	-rw-r--r--	2021-11-01 05:53
fault-inject.h	1.93 KB	-rw-r--r--	2021-11-01 05:53
fb.h	28.28 KB	-rw-r--r--	2026-06-20 00:54
fbcon.h	2.09 KB	-rw-r--r--	2026-06-20 00:54
fcdevice.h	774 B	-rw-r--r--	2021-11-01 05:53
fcntl.h	1.66 KB	-rw-r--r--	2021-11-01 05:53
fd.h	490 B	-rw-r--r--	2021-11-01 05:53
fddidevice.h	833 B	-rw-r--r--	2021-11-01 05:53
fdtable.h	3.49 KB	-rw-r--r--	2026-06-20 00:54
fec.h	463 B	-rw-r--r--	2021-11-01 05:53
fiemap.h	713 B	-rw-r--r--	2021-11-01 05:53
file.h	3.08 KB	-rw-r--r--	2026-06-20 00:54
fileattr.h	1.91 KB	-rw-r--r--	2021-11-01 05:53
filter.h	42.96 KB	-rw-r--r--	2026-06-20 00:54
fips.h	303 B	-rw-r--r--	2021-11-01 05:53
firewire.h	13.4 KB	-rw-r--r--	2021-11-01 05:53
firmware-map.h	959 B	-rw-r--r--	2021-11-01 05:53
firmware.h	3.27 KB	-rw-r--r--	2021-11-01 05:53
fixp-arith.h	4.19 KB	-rw-r--r--	2021-11-01 05:53
flat.h	2.57 KB	-rw-r--r--	2021-11-01 05:53
flex_proportions.h	2.81 KB	-rw-r--r--	2021-11-01 05:53
font.h	1.67 KB	-rw-r--r--	2021-11-01 05:53
fortify-string.h	9.11 KB	-rw-r--r--	2026-06-20 00:54
freelist.h	3.8 KB	-rw-r--r--	2021-11-01 05:53
freezer.h	8.98 KB	-rw-r--r--	2021-11-01 05:53
frontswap.h	3.04 KB	-rw-r--r--	2021-11-01 05:53
fs.h	122.56 KB	-rw-r--r--	2026-06-20 00:54
fs_context.h	8.61 KB	-rw-r--r--	2026-06-20 00:54
fs_enet_pd.h	3.38 KB	-rw-r--r--	2021-11-01 05:53
fs_parser.h	4.44 KB	-rw-r--r--	2021-11-01 05:53
fs_pin.h	539 B	-rw-r--r--	2021-11-01 05:53
fs_stack.h	811 B	-rw-r--r--	2021-11-01 05:53
fs_struct.h	1.04 KB	-rw-r--r--	2021-11-01 05:53
fs_types.h	2.02 KB	-rw-r--r--	2021-11-01 05:53
fs_uart_pd.h	1.49 KB	-rw-r--r--	2021-11-01 05:53
fscache-cache.h	18.58 KB	-rw-r--r--	2021-11-01 05:53
fscache.h	29.59 KB	-rw-r--r--	2026-06-20 00:54
fscrypt.h	29.9 KB	-rw-r--r--	2026-06-20 00:54
fsi-occ.h	681 B	-rw-r--r--	2021-11-01 05:53
fsi-sbefifo.h	629 B	-rw-r--r--	2021-11-01 05:53
fsi.h	2.26 KB	-rw-r--r--	2021-11-01 05:53
fsl-diu-fb.h	3.87 KB	-rw-r--r--	2021-11-01 05:53
fsl_devices.h	4.16 KB	-rw-r--r--	2021-11-01 05:53
fsl_hypervisor.h	2.76 KB	-rw-r--r--	2021-11-01 05:53
fsl_ifc.h	24.48 KB	-rw-r--r--	2021-11-01 05:53
fsldma.h	202 B	-rw-r--r--	2021-11-01 05:53
fsnotify.h	10.05 KB	-rw-r--r--	2026-06-20 00:54
fsnotify_backend.h	29.3 KB	-rw-r--r--	2026-06-20 00:54
fsverity.h	6.75 KB	-rw-r--r--	2021-11-01 05:53
ftrace.h	34.76 KB	-rw-r--r--	2026-06-20 00:54
ftrace_irq.h	884 B	-rw-r--r--	2021-11-01 05:53
futex.h	2.44 KB	-rw-r--r--	2021-11-01 05:53
fwnode.h	6.83 KB	-rw-r--r--	2026-06-20 00:54
fwnode_mdio.h	858 B	-rw-r--r--	2021-11-01 05:53
gameport.h	5.42 KB	-rw-r--r--	2021-11-01 05:53
gcd.h	193 B	-rw-r--r--	2021-11-01 05:53
genalloc.h	7.73 KB	-rw-r--r--	2026-06-20 00:54
generic-radix-tree.h	6.35 KB	-rw-r--r--	2021-11-01 05:53
genetlink.h	589 B	-rw-r--r--	2021-11-01 05:53
genhd.h	8.84 KB	-rw-r--r--	2026-06-20 00:54
genl_magic_func.h	11.53 KB	-rw-r--r--	2021-11-01 05:53
genl_magic_struct.h	7.61 KB	-rw-r--r--	2021-11-01 05:53
getcpu.h	641 B	-rw-r--r--	2021-11-01 05:53
gfp.h	26.26 KB	-rw-r--r--	2026-06-20 00:54
glob.h	256 B	-rw-r--r--	2021-11-01 05:53
gnss.h	1.56 KB	-rw-r--r--	2021-11-01 05:53
goldfish.h	878 B	-rw-r--r--	2026-06-20 00:54
gpio-pxa.h	571 B	-rw-r--r--	2021-11-01 05:53
gpio.h	5.3 KB	-rw-r--r--	2021-11-01 05:53
gpio_keys.h	1.74 KB	-rw-r--r--	2021-11-01 05:53
greybus.h	4.14 KB	-rw-r--r--	2021-11-01 05:53
hardirq.h	3.43 KB	-rw-r--r--	2021-11-01 05:53
hash.h	3 KB	-rw-r--r--	2021-11-01 05:53
hashtable.h	6.67 KB	-rw-r--r--	2021-11-01 05:53
hdlc.h	3.19 KB	-rw-r--r--	2021-11-01 05:53
hdlcdrv.h	6.32 KB	-rw-r--r--	2021-11-01 05:53
hdmi.h	12.41 KB	-rw-r--r--	2021-11-01 05:53
hid-debug.h	1.42 KB	-rw-r--r--	2021-11-01 05:53
hid-roccat.h	484 B	-rw-r--r--	2021-11-01 05:53
hid-sensor-hub.h	8.97 KB	-rw-r--r--	2021-11-01 05:53
hid-sensor-ids.h	7.44 KB	-rw-r--r--	2021-11-01 05:53
hid.h	38.01 KB	-rw-r--r--	2026-06-20 00:54
hidden.h	966 B	-rw-r--r--	2021-11-01 05:53
hiddev.h	1.42 KB	-rw-r--r--	2021-11-01 05:53
hidraw.h	1.12 KB	-rw-r--r--	2021-11-01 05:53
highmem-internal.h	5.12 KB	-rw-r--r--	2026-06-20 00:54
highmem.h	9.5 KB	-rw-r--r--	2026-06-20 00:54
highuid.h	3.12 KB	-rw-r--r--	2021-11-01 05:53
hil.h	18.42 KB	-rw-r--r--	2021-11-01 05:53
hil_mlc.h	5.13 KB	-rw-r--r--	2021-11-01 05:53
hippidevice.h	1.03 KB	-rw-r--r--	2021-11-01 05:53
hmm.h	4.07 KB	-rw-r--r--	2021-11-01 05:53
host1x.h	10.74 KB	-rw-r--r--	2021-11-01 05:53
hp_sdc.h	14.02 KB	-rw-r--r--	2021-11-01 05:53
hpet.h	2.55 KB	-rw-r--r--	2021-11-01 05:53
hrtimer.h	16.13 KB	-rw-r--r--	2026-06-20 00:54
hrtimer_defs.h	660 B	-rw-r--r--	2021-11-01 05:53
htcpld.h	617 B	-rw-r--r--	2021-11-01 05:53
huge_mm.h	13.27 KB	-rw-r--r--	2021-11-01 05:53
hugetlb.h	29.7 KB	-rw-r--r--	2026-06-20 00:54
hugetlb_cgroup.h	7.07 KB	-rw-r--r--	2021-11-01 05:53
hugetlb_inline.h	374 B	-rw-r--r--	2021-11-01 05:53
hw_breakpoint.h	4.15 KB	-rw-r--r--	2021-11-01 05:53
hw_random.h	2.12 KB	-rw-r--r--	2026-06-20 00:54
hwmon-sysfs.h	2.77 KB	-rw-r--r--	2021-11-01 05:53
hwmon-vid.h	862 B	-rw-r--r--	2021-11-01 05:53
hwmon.h	14.78 KB	-rw-r--r--	2021-11-01 05:53
hwspinlock.h	15.79 KB	-rw-r--r--	2026-06-20 00:54
hyperv.h	49.04 KB	-rw-r--r--	2026-06-20 00:54
hypervisor.h	608 B	-rw-r--r--	2021-11-01 05:53
i2c-algo-bit.h	1.4 KB	-rw-r--r--	2021-11-01 05:53
i2c-algo-pca.h	2.89 KB	-rw-r--r--	2021-11-01 05:53
i2c-algo-pcf.h	1.21 KB	-rw-r--r--	2021-11-01 05:53
i2c-dev.h	371 B	-rw-r--r--	2021-11-01 05:53
i2c-mux.h	1.63 KB	-rw-r--r--	2021-11-01 05:53
i2c-smbus.h	1.7 KB	-rw-r--r--	2026-06-20 00:54
i2c.h	38.6 KB	-rw-r--r--	2026-06-20 00:54
i8042.h	1.99 KB	-rw-r--r--	2021-11-01 05:53
i8253.h	808 B	-rw-r--r--	2026-06-20 00:54
icmp.h	1 KB	-rw-r--r--	2021-11-01 05:53
icmpv6.h	2.7 KB	-rw-r--r--	2021-11-01 05:53
idle_inject.h	932 B	-rw-r--r--	2021-11-01 05:53
idr.h	9.7 KB	-rw-r--r--	2026-06-20 00:54
ieee80211.h	124.15 KB	-rw-r--r--	2026-06-20 00:54
ieee802154.h	11.12 KB	-rw-r--r--	2021-11-01 05:53
if_arp.h	1.81 KB	-rw-r--r--	2026-06-20 00:54
if_bridge.h	4.8 KB	-rw-r--r--	2026-06-20 00:54
if_eql.h	1.07 KB	-rw-r--r--	2021-11-01 05:53
if_ether.h	1.26 KB	-rw-r--r--	2021-11-01 05:53
if_fddi.h	3.24 KB	-rw-r--r--	2021-11-01 05:53
if_hsr.h	586 B	-rw-r--r--	2021-11-01 05:53
if_link.h	592 B	-rw-r--r--	2021-11-01 05:53
if_ltalk.h	188 B	-rw-r--r--	2021-11-01 05:53
if_macvlan.h	2.69 KB	-rw-r--r--	2021-11-01 05:53
if_phonet.h	319 B	-rw-r--r--	2021-11-01 05:53
if_pppol2tp.h	516 B	-rw-r--r--	2021-11-01 05:53
if_pppox.h	2.84 KB	-rw-r--r--	2021-11-01 05:53
if_rmnet.h	2.04 KB	-rw-r--r--	2021-11-01 05:53
if_tap.h	2.21 KB	-rw-r--r--	2021-11-01 05:53
if_team.h	7.9 KB	-rw-r--r--	2026-06-20 00:54
if_tun.h	1.55 KB	-rw-r--r--	2021-11-01 05:53
if_tunnel.h	409 B	-rw-r--r--	2021-11-01 05:53
if_vlan.h	21.18 KB	-rw-r--r--	2026-06-20 00:54
igmp.h	4.31 KB	-rw-r--r--	2026-06-20 00:54
ihex.h	2.15 KB	-rw-r--r--	2021-11-01 05:53
ima.h	5.79 KB	-rw-r--r--	2026-06-20 00:54
imx-media.h	605 B	-rw-r--r--	2021-11-01 05:53
in.h	2.29 KB	-rw-r--r--	2021-11-01 05:53
in6.h	1.63 KB	-rw-r--r--	2021-11-01 05:53
indirect_call_wrapper.h	2.23 KB	-rw-r--r--	2021-11-01 05:53
inet.h	2.64 KB	-rw-r--r--	2021-11-01 05:53
inet_diag.h	2.74 KB	-rw-r--r--	2021-11-01 05:53
inetdevice.h	8.87 KB	-rw-r--r--	2021-11-01 05:53
init.h	11.39 KB	-rw-r--r--	2021-11-01 05:53
init_ohci1394_dma.h	196 B	-rw-r--r--	2021-11-01 05:53
init_syscalls.h	1.01 KB	-rw-r--r--	2021-11-01 05:53
init_task.h	1.3 KB	-rw-r--r--	2021-11-01 05:53
initrd.h	1.02 KB	-rw-r--r--	2021-11-01 05:53
inotify.h	713 B	-rw-r--r--	2021-11-01 05:53
input.h	19.88 KB	-rw-r--r--	2021-11-01 05:53
instrumentation.h	1.93 KB	-rw-r--r--	2026-06-20 00:54
instrumented.h	3.6 KB	-rw-r--r--	2021-11-01 05:53
integrity.h	1.15 KB	-rw-r--r--	2021-11-01 05:53
intel-iommu.h	27.28 KB	-rw-r--r--	2026-06-20 00:54
intel-ish-client-if.h	3.97 KB	-rw-r--r--	2021-11-01 05:53
intel-svm.h	1.54 KB	-rw-r--r--	2021-11-01 05:53
intel_rapl.h	4.14 KB	-rw-r--r--	2021-11-01 05:53
intel_th.h	2.44 KB	-rw-r--r--	2021-11-01 05:53
interconnect-provider.h	5.51 KB	-rw-r--r--	2021-11-01 05:53
interconnect.h	2.88 KB	-rw-r--r--	2021-11-01 05:53
interrupt.h	25.23 KB	-rw-r--r--	2026-06-20 00:54
interval_tree.h	831 B	-rw-r--r--	2021-11-01 05:53
interval_tree_generic.h	6.7 KB	-rw-r--r--	2021-11-01 05:53
io-64-nonatomic-hi-lo.h	2.41 KB	-rw-r--r--	2021-11-01 05:53
io-64-nonatomic-lo-hi.h	2.41 KB	-rw-r--r--	2021-11-01 05:53
io-mapping.h	4.65 KB	-rw-r--r--	2021-11-01 05:53
io-pgtable.h	8.65 KB	-rw-r--r--	2026-06-20 00:54
io.h	5.02 KB	-rw-r--r--	2021-11-01 05:53
io_uring.h	881 B	-rw-r--r--	2026-06-20 00:54
ioam6.h	226 B	-rw-r--r--	2021-11-01 05:53
ioam6_genl.h	266 B	-rw-r--r--	2021-11-01 05:53
ioam6_iptunnel.h	285 B	-rw-r--r--	2021-11-01 05:53
ioasid.h	2.07 KB	-rw-r--r--	2021-11-01 05:53
iocontext.h	4.59 KB	-rw-r--r--	2021-11-01 05:53
iomap.h	11.91 KB	-rw-r--r--	2026-06-20 00:54
iommu-helper.h	1.12 KB	-rw-r--r--	2021-11-01 05:53
iommu.h	34.06 KB	-rw-r--r--	2026-06-20 00:54
iopoll.h	7.61 KB	-rw-r--r--	2026-06-20 00:54
ioport.h	12.28 KB	-rw-r--r--	2026-06-20 00:54
ioprio.h	1.73 KB	-rw-r--r--	2026-06-20 00:54
iova.h	6.19 KB	-rw-r--r--	2026-06-20 00:54
ip.h	1 KB	-rw-r--r--	2021-11-01 05:53
ipack.h	8.69 KB	-rw-r--r--	2021-11-01 05:53
ipc.h	613 B	-rw-r--r--	2021-11-01 05:53
ipc_namespace.h	5.63 KB	-rw-r--r--	2026-06-20 00:54
ipmi.h	10.88 KB	-rw-r--r--	2021-11-01 05:53
ipmi_smi.h	7.98 KB	-rw-r--r--	2021-11-01 05:53
ipv6.h	8.7 KB	-rw-r--r--	2026-06-20 00:54
ipv6_route.h	372 B	-rw-r--r--	2021-11-01 05:53
irq.h	41.76 KB	-rw-r--r--	2026-06-20 00:54
irq_poll.h	575 B	-rw-r--r--	2021-11-01 05:53
irq_sim.h	789 B	-rw-r--r--	2021-11-01 05:53
irq_work.h	1.82 KB	-rw-r--r--	2026-06-20 00:54
irqbypass.h	3.45 KB	-rw-r--r--	2021-11-01 05:53
irqchip.h	2.33 KB	-rw-r--r--	2021-11-01 05:53
irqdesc.h	7.75 KB	-rw-r--r--	2021-11-01 05:53
irqdomain.h	20.24 KB	-rw-r--r--	2026-06-20 00:54
irqflags.h	7.91 KB	-rw-r--r--	2026-06-20 00:54
irqhandler.h	300 B	-rw-r--r--	2021-11-01 05:53
irqnr.h	856 B	-rw-r--r--	2021-11-01 05:53
irqreturn.h	503 B	-rw-r--r--	2021-11-01 05:53
isa.h	2.12 KB	-rw-r--r--	2021-11-01 05:53
isapnp.h	2.88 KB	-rw-r--r--	2021-11-01 05:53
iscsi_boot_sysfs.h	3.71 KB	-rw-r--r--	2021-11-01 05:53
iscsi_ibft.h	847 B	-rw-r--r--	2021-11-01 05:53
iversion.h	12.37 KB	-rw-r--r--	2021-11-01 05:53
jbd2.h	51.2 KB	-rw-r--r--	2026-06-20 00:54
jhash.h	4.56 KB	-rw-r--r--	2021-11-01 05:53
jiffies.h	15.07 KB	-rw-r--r--	2026-06-20 00:54
journal-head.h	2.91 KB	-rw-r--r--	2021-11-01 05:53
joystick.h	437 B	-rw-r--r--	2021-11-01 05:53
jump_label.h	16.05 KB	-rw-r--r--	2026-06-20 00:54
jump_label_ratelimit.h	2.77 KB	-rw-r--r--	2021-11-01 05:53
jz4740-adc.h	1023 B	-rw-r--r--	2021-11-01 05:53
jz4780-nemc.h	976 B	-rw-r--r--	2021-11-01 05:53
kallsyms.h	4.65 KB	-rw-r--r--	2026-06-20 00:54
kasan-checks.h	1.46 KB	-rw-r--r--	2021-11-01 05:53
kasan-tags.h	487 B	-rw-r--r--	2021-11-01 05:53
kasan.h	13.4 KB	-rw-r--r--	2026-06-20 00:54
kbd_diacr.h	198 B	-rw-r--r--	2021-11-01 05:53
kbd_kern.h	3.6 KB	-rw-r--r--	2021-11-01 05:53
kbuild.h	380 B	-rw-r--r--	2021-11-01 05:53
kconfig.h	2.63 KB	-rw-r--r--	2021-11-01 05:53
kcore.h	891 B	-rw-r--r--	2021-11-01 05:53
kcov.h	2.48 KB	-rw-r--r--	2026-06-20 00:54
kcsan-checks.h	15.86 KB	-rw-r--r--	2021-11-01 05:53
kcsan.h	1.88 KB	-rw-r--r--	2021-11-01 05:53
kdb.h	7.33 KB	-rw-r--r--	2021-11-01 05:53
kdebug.h	487 B	-rw-r--r--	2021-11-01 05:53
kdev_t.h	1.8 KB	-rw-r--r--	2021-11-01 05:53
kern_levels.h	1.57 KB	-rw-r--r--	2021-11-01 05:53
kernel-page-flags.h	528 B	-rw-r--r--	2021-11-01 05:53
kernel.h	17.01 KB	-rw-r--r--	2026-06-20 00:54
kernel_read_file.h	1.64 KB	-rw-r--r--	2021-11-01 05:53
kernel_stat.h	2.97 KB	-rw-r--r--	2026-06-20 00:54
kernelcapi.h	1.45 KB	-rw-r--r--	2021-11-01 05:53
kernfs.h	18.25 KB	-rw-r--r--	2026-06-20 00:54
kexec.h	12.44 KB	-rw-r--r--	2026-06-20 00:54
key-type.h	6.63 KB	-rw-r--r--	2026-06-20 00:54
key.h	15.75 KB	-rw-r--r--	2021-11-01 05:53
keyboard.h	665 B	-rw-r--r--	2021-11-01 05:53
keyctl.h	1.25 KB	-rw-r--r--	2021-11-01 05:53
keyslot-manager.h	3.78 KB	-rw-r--r--	2021-11-01 05:53
kfence.h	8.56 KB	-rw-r--r--	2026-06-20 00:54
kfifo.h	26.18 KB	-rw-r--r--	2026-06-20 00:54
kgdb.h	12.05 KB	-rw-r--r--	2021-11-01 05:53
khugepaged.h	2.74 KB	-rw-r--r--	2021-11-01 05:53
klist.h	1.88 KB	-rw-r--r--	2021-11-01 05:53
kmemleak.h	3.27 KB	-rw-r--r--	2021-11-01 05:53
kmod.h	1.02 KB	-rw-r--r--	2021-11-01 05:53
kmsg_dump.h	2.71 KB	-rw-r--r--	2021-11-01 05:53
kobj_map.h	545 B	-rw-r--r--	2021-11-01 05:53
kobject.h	7.7 KB	-rw-r--r--	2026-06-20 00:54
kobject_ns.h	1.9 KB	-rw-r--r--	2021-11-01 05:53
kprobes.h	14.72 KB	-rw-r--r--	2026-06-20 00:54
kref.h	3.08 KB	-rw-r--r--	2021-11-01 05:53
ks0108.h	970 B	-rw-r--r--	2021-11-01 05:53
ks8842.h	632 B	-rw-r--r--	2021-11-01 05:53
ks8851_mll.h	472 B	-rw-r--r--	2021-11-01 05:53
ksm.h	2.47 KB	-rw-r--r--	2021-11-01 05:53
kstrtox.h	6.59 KB	-rw-r--r--	2021-11-01 05:53
kthread.h	7.69 KB	-rw-r--r--	2026-06-20 00:54
ktime.h	5.38 KB	-rw-r--r--	2021-11-01 05:53
kvm_dirty_ring.h	2.73 KB	-rw-r--r--	2021-11-01 05:53
kvm_host.h	58.61 KB	-rw-r--r--	2026-06-20 00:54
kvm_irqfd.h	2 KB	-rw-r--r--	2021-11-01 05:53
kvm_para.h	402 B	-rw-r--r--	2021-11-01 05:53
kvm_types.h	2.17 KB	-rw-r--r--	2021-11-01 05:53
l2tp.h	261 B	-rw-r--r--	2021-11-01 05:53
lantiq.h	365 B	-rw-r--r--	2021-11-01 05:53
lapb.h	1.71 KB	-rw-r--r--	2021-11-01 05:53
latencytop.h	1.16 KB	-rw-r--r--	2021-11-01 05:53
lcd.h	3.78 KB	-rw-r--r--	2021-11-01 05:53
lcm.h	275 B	-rw-r--r--	2021-11-01 05:53
led-class-flash.h	6.74 KB	-rw-r--r--	2021-11-01 05:53
led-class-multicolor.h	3.26 KB	-rw-r--r--	2021-11-01 05:53
led-lm3530.h	3.7 KB	-rw-r--r--	2021-11-01 05:53
leds-bd2802.h	476 B	-rw-r--r--	2021-11-01 05:53
leds-lp3944.h	950 B	-rw-r--r--	2021-11-01 05:53
leds-lp3952.h	2.35 KB	-rw-r--r--	2021-11-01 05:53
leds-pca9532.h	866 B	-rw-r--r--	2021-11-01 05:53
leds-regulator.h	1.14 KB	-rw-r--r--	2021-11-01 05:53
leds-ti-lmu-common.h	1.12 KB	-rw-r--r--	2021-11-01 05:53
leds.h	18.06 KB	-rw-r--r--	2026-06-20 00:54
libata.h	67.43 KB	-rw-r--r--	2026-06-20 00:54
libfdt.h	202 B	-rw-r--r--	2021-11-01 05:53
libfdt_env.h	491 B	-rw-r--r--	2021-11-01 05:53
libgcc.h	463 B	-rw-r--r--	2021-11-01 05:53
libnvdimm.h	10.38 KB	-rw-r--r--	2021-11-01 05:53
libps2.h	1.89 KB	-rw-r--r--	2021-11-01 05:53
license.h	418 B	-rw-r--r--	2021-11-01 05:53
limits.h	715 B	-rw-r--r--	2021-11-01 05:53
linear_range.h	1.72 KB	-rw-r--r--	2021-11-01 05:53
linkage.h	9.6 KB	-rw-r--r--	2026-06-20 00:54
linkmode.h	2.5 KB	-rw-r--r--	2021-11-01 05:53
linux_logo.h	1.91 KB	-rw-r--r--	2021-11-01 05:53
lis3lv02d.h	5 KB	-rw-r--r--	2021-11-01 05:53
list.h	30.47 KB	-rw-r--r--	2026-06-20 00:54
list_bl.h	4.79 KB	-rw-r--r--	2021-11-01 05:53
list_lru.h	7.29 KB	-rw-r--r--	2021-11-01 05:53
list_nulls.h	4.22 KB	-rw-r--r--	2021-11-01 05:53
list_sort.h	374 B	-rw-r--r--	2021-11-01 05:53
litex.h	2.06 KB	-rw-r--r--	2021-11-01 05:53
livepatch.h	8.22 KB	-rw-r--r--	2021-11-01 05:53
llc.h	749 B	-rw-r--r--	2021-11-01 05:53
llist.h	9.06 KB	-rw-r--r--	2021-11-01 05:53
local_lock.h	1.33 KB	-rw-r--r--	2021-11-01 05:53
local_lock_internal.h	3.42 KB	-rw-r--r--	2021-11-01 05:53
lockdep.h	21.49 KB	-rw-r--r--	2026-06-20 00:54
lockdep_types.h	5.18 KB	-rw-r--r--	2021-11-01 05:53
lockref.h	1.5 KB	-rw-r--r--	2021-11-01 05:53
log2.h	6.22 KB	-rw-r--r--	2021-11-01 05:53
logic_iomem.h	2.07 KB	-rw-r--r--	2021-11-01 05:53
logic_pio.h	3.23 KB	-rw-r--r--	2021-11-01 05:53
lp.h	2.76 KB	-rw-r--r--	2021-11-01 05:53
lru_cache.h	11.83 KB	-rw-r--r--	2021-11-01 05:53
lsm_audit.h	2.81 KB	-rw-r--r--	2021-11-01 05:53
lsm_hook_defs.h	21.01 KB	-rw-r--r--	2026-06-20 00:54
lsm_hooks.h	74.39 KB	-rw-r--r--	2026-06-20 00:54
lz4.h	26.44 KB	-rw-r--r--	2021-11-01 05:53
lzo.h	1.93 KB	-rw-r--r--	2026-06-20 00:54
mISDNdsp.h	1.19 KB	-rw-r--r--	2021-11-01 05:53
mISDNhw.h	5.39 KB	-rw-r--r--	2021-11-01 05:53
mISDNif.h	14.89 KB	-rw-r--r--	2021-11-01 05:53
mailbox_client.h	1.71 KB	-rw-r--r--	2021-11-01 05:53
mailbox_controller.h	5.7 KB	-rw-r--r--	2026-06-20 00:54
maple.h	2.71 KB	-rw-r--r--	2021-11-01 05:53
marvell_phy.h	1.69 KB	-rw-r--r--	2021-11-01 05:53
math.h	5.06 KB	-rw-r--r--	2021-11-01 05:53
math64.h	7.48 KB	-rw-r--r--	2021-11-01 05:53
mbcache.h	2.16 KB	-rw-r--r--	2026-06-20 00:54
mbus.h	3.09 KB	-rw-r--r--	2021-11-01 05:53
mc146818rtc.h	4.69 KB	-rw-r--r--	2026-06-20 00:54
mc6821.h	1.18 KB	-rw-r--r--	2021-11-01 05:53
mcb.h	3.71 KB	-rw-r--r--	2026-06-20 00:54
mdev.h	5.94 KB	-rw-r--r--	2021-11-01 05:53
mdio-bitbang.h	1.31 KB	-rw-r--r--	2021-11-01 05:53
mdio-gpio.h	177 B	-rw-r--r--	2021-11-01 05:53
mdio-mux.h	1021 B	-rw-r--r--	2021-11-01 05:53
mdio.h	12.69 KB	-rw-r--r--	2026-06-20 00:54
mei_cl_bus.h	3.75 KB	-rw-r--r--	2021-11-01 05:53
mem_encrypt.h	885 B	-rw-r--r--	2021-11-01 05:53
memblock.h	19.88 KB	-rw-r--r--	2026-06-20 00:54
memcontrol.h	43.58 KB	-rw-r--r--	2026-06-20 00:54
memfd.h	719 B	-rw-r--r--	2026-06-20 00:54
memory.h	5.99 KB	-rw-r--r--	2021-11-01 05:53
memory_hotplug.h	11.42 KB	-rw-r--r--	2021-11-01 05:53
mempolicy.h	7.37 KB	-rw-r--r--	2021-11-01 05:53
mempool.h	3.35 KB	-rw-r--r--	2021-11-01 05:53
memregion.h	417 B	-rw-r--r--	2026-06-20 00:54
memremap.h	5.61 KB	-rw-r--r--	2026-06-20 00:54
memstick.h	9.6 KB	-rw-r--r--	2021-11-01 05:53
mhi.h	26.04 KB	-rw-r--r--	2026-06-20 00:54
micrel_phy.h	1.84 KB	-rw-r--r--	2026-06-20 00:54
microchipphy.h	2.65 KB	-rw-r--r--	2021-11-01 05:53
migrate.h	5.41 KB	-rw-r--r--	2021-11-01 05:53
migrate_mode.h	758 B	-rw-r--r--	2021-11-01 05:53
mii.h	16.33 KB	-rw-r--r--	2021-11-01 05:53
mii_timestamper.h	3.57 KB	-rw-r--r--	2021-11-01 05:53
min_heap.h	3.3 KB	-rw-r--r--	2021-11-01 05:53
minmax.h	10 KB	-rw-r--r--	2026-06-20 00:54
misc_cgroup.h	2.95 KB	-rw-r--r--	2021-11-01 05:53
miscdevice.h	3.2 KB	-rw-r--r--	2021-11-01 05:53
mm.h	105.69 KB	-rw-r--r--	2026-06-20 00:54
mm_inline.h	2.92 KB	-rw-r--r--	2021-11-01 05:53
mm_types.h	25.13 KB	-rw-r--r--	2026-06-20 00:54
mm_types_task.h	2.5 KB	-rw-r--r--	2021-11-01 05:53
mman.h	3.96 KB	-rw-r--r--	2026-06-20 00:54
mmap_lock.h	4.25 KB	-rw-r--r--	2021-11-01 05:53
mmdebug.h	2.25 KB	-rw-r--r--	2021-11-01 05:53
mmiotrace.h	3.05 KB	-rw-r--r--	2021-11-01 05:53
mmu_context.h	855 B	-rw-r--r--	2021-11-01 05:53
mmu_notifier.h	24.64 KB	-rw-r--r--	2021-11-01 05:53
mmzone.h	47.39 KB	-rw-r--r--	2026-06-20 00:54
mnt_idmapping.h	7.65 KB	-rw-r--r--	2026-06-20 00:54
mnt_namespace.h	697 B	-rw-r--r--	2026-06-20 00:54
mod_devicetable.h	23.5 KB	-rw-r--r--	2026-06-20 00:54
module.h	23.96 KB	-rw-r--r--	2026-06-20 00:54
module_signature.h	1.22 KB	-rw-r--r--	2021-11-01 05:53
moduleloader.h	3.42 KB	-rw-r--r--	2026-06-20 00:54
moduleparam.h	22.35 KB	-rw-r--r--	2026-06-20 00:54
most.h	12.2 KB	-rw-r--r--	2021-11-01 05:53
mount.h	3.93 KB	-rw-r--r--	2021-11-01 05:53
moxtet.h	2.36 KB	-rw-r--r--	2021-11-01 05:53
mpage.h	737 B	-rw-r--r--	2021-11-01 05:53
mpi.h	8.41 KB	-rw-r--r--	2021-11-01 05:53
mpls.h	394 B	-rw-r--r--	2021-11-01 05:53
mpls_iptunnel.h	178 B	-rw-r--r--	2021-11-01 05:53
mroute.h	1.96 KB	-rw-r--r--	2026-06-20 00:54
mroute6.h	2.41 KB	-rw-r--r--	2021-11-01 05:53
mroute_base.h	12.17 KB	-rw-r--r--	2021-11-01 05:53
msdos_fs.h	273 B	-rw-r--r--	2021-11-01 05:53
msdos_partition.h	1.62 KB	-rw-r--r--	2021-11-01 05:53
msg.h	395 B	-rw-r--r--	2021-11-01 05:53
msi.h	15.36 KB	-rw-r--r--	2026-06-20 00:54
mtio.h	1.29 KB	-rw-r--r--	2021-11-01 05:53
mutex.h	7.31 KB	-rw-r--r--	2026-06-20 00:54
mv643xx.h	51.05 KB	-rw-r--r--	2021-11-01 05:53
mv643xx_eth.h	1.95 KB	-rw-r--r--	2021-11-01 05:53
mv643xx_i2c.h	335 B	-rw-r--r--	2021-11-01 05:53
mvebu-pmsu.h	520 B	-rw-r--r--	2021-11-01 05:53
mxm-wmi.h	399 B	-rw-r--r--	2021-11-01 05:53
namei.h	4.57 KB	-rw-r--r--	2026-06-20 00:54
nd.h	5.55 KB	-rw-r--r--	2021-11-01 05:53
ndctl.h	674 B	-rw-r--r--	2021-11-01 05:53
net.h	11.47 KB	-rw-r--r--	2026-06-20 00:54
netdev_features.h	10.75 KB	-rw-r--r--	2026-06-20 00:54
netdevice.h	168.73 KB	-rw-r--r--	2026-06-20 00:54
netfilter.h	13.56 KB	-rw-r--r--	2026-06-20 00:54
netfilter_bridge.h	2.08 KB	-rw-r--r--	2021-11-01 05:53
netfilter_defs.h	242 B	-rw-r--r--	2026-06-20 00:54
netfilter_ingress.h	1.44 KB	-rw-r--r--	2021-11-01 05:53
netfilter_ipv4.h	1.05 KB	-rw-r--r--	2021-11-01 05:53
netfilter_ipv6.h	5.85 KB	-rw-r--r--	2021-11-01 05:53
netfs.h	7.93 KB	-rw-r--r--	2021-11-01 05:53
netlink.h	7.88 KB	-rw-r--r--	2021-11-01 05:53
netpoll.h	2.42 KB	-rw-r--r--	2026-06-20 00:54
nfs.h	1.47 KB	-rw-r--r--	2026-06-20 00:54
nfs3.h	260 B	-rw-r--r--	2021-11-01 05:53
nfs4.h	19.37 KB	-rw-r--r--	2026-06-20 00:54
nfs_common.h	402 B	-rw-r--r--	2026-06-20 00:54
nfs_fs.h	20.39 KB	-rw-r--r--	2026-06-20 00:54
nfs_fs_i.h	308 B	-rw-r--r--	2021-11-01 05:53
nfs_fs_sb.h	10.25 KB	-rw-r--r--	2026-06-20 00:54
nfs_iostat.h	4.18 KB	-rw-r--r--	2021-11-01 05:53
nfs_page.h	6.8 KB	-rw-r--r--	2026-06-20 00:54
nfs_ssc.h	2.01 KB	-rw-r--r--	2026-06-20 00:54
nfs_xdr.h	42.26 KB	-rw-r--r--	2026-06-20 00:54
nfsacl.h	1.4 KB	-rw-r--r--	2021-11-01 05:53
nitro_enclaves.h	267 B	-rw-r--r--	2021-11-01 05:53
nl802154.h	3.85 KB	-rw-r--r--	2021-11-01 05:53
nls.h	3.09 KB	-rw-r--r--	2026-06-20 00:54
nmi.h	6.76 KB	-rw-r--r--	2026-06-20 00:54
node.h	4.67 KB	-rw-r--r--	2021-11-01 05:53
nodemask.h	17.17 KB	-rw-r--r--	2026-06-20 00:54
nospec.h	2.24 KB	-rw-r--r--	2026-06-20 00:54
notifier.h	7.84 KB	-rw-r--r--	2021-11-01 05:53
ns_common.h	283 B	-rw-r--r--	2021-11-01 05:53
nsc_gpio.h	1.42 KB	-rw-r--r--	2021-11-01 05:53
nsproxy.h	3.09 KB	-rw-r--r--	2021-11-01 05:53
ntb.h	52.43 KB	-rw-r--r--	2021-11-01 05:53
ntb_transport.h	3.8 KB	-rw-r--r--	2021-11-01 05:53
nubus.h	5.54 KB	-rw-r--r--	2021-11-01 05:53
numa.h	1.25 KB	-rw-r--r--	2021-11-01 05:53
nvme-fc-driver.h	45.86 KB	-rw-r--r--	2021-11-01 05:53
nvme-fc.h	9.72 KB	-rw-r--r--	2021-11-01 05:53
nvme-rdma.h	2.04 KB	-rw-r--r--	2021-11-01 05:53
nvme-tcp.h	4.42 KB	-rw-r--r--	2026-06-20 00:54
nvme.h	38.32 KB	-rw-r--r--	2026-06-20 00:54
nvmem-consumer.h	6.78 KB	-rw-r--r--	2021-11-01 05:53
nvmem-provider.h	4.66 KB	-rw-r--r--	2026-06-20 00:54
nvram.h	3.47 KB	-rw-r--r--	2021-11-01 05:53
objagg.h	1.94 KB	-rw-r--r--	2026-06-20 00:54
objtool.h	5.24 KB	-rw-r--r--	2026-06-20 00:54
of.h	43.4 KB	-rw-r--r--	2026-06-20 00:54
of_address.h	4.17 KB	-rw-r--r--	2021-11-01 05:53
of_clk.h	819 B	-rw-r--r--	2021-11-01 05:53
of_device.h	2.96 KB	-rw-r--r--	2026-06-20 00:54
of_dma.h	2.3 KB	-rw-r--r--	2021-11-01 05:53
of_fdt.h	3.65 KB	-rw-r--r--	2026-06-20 00:54
of_gpio.h	4.07 KB	-rw-r--r--	2021-11-01 05:53
of_graph.h	3.55 KB	-rw-r--r--	2021-11-01 05:53
of_iommu.h	505 B	-rw-r--r--	2021-11-01 05:53
of_irq.h	3.75 KB	-rw-r--r--	2021-11-01 05:53
of_mdio.h	3.91 KB	-rw-r--r--	2026-06-20 00:54
of_net.h	1009 B	-rw-r--r--	2026-06-20 00:54
of_pci.h	915 B	-rw-r--r--	2021-11-01 05:53
of_pdt.h	1.14 KB	-rw-r--r--	2021-11-01 05:53
of_platform.h	3.88 KB	-rw-r--r--	2021-11-01 05:53
of_reserved_mem.h	2.24 KB	-rw-r--r--	2021-11-01 05:53
oid_registry.h	5.63 KB	-rw-r--r--	2021-11-01 05:53
olpc-ec.h	1.95 KB	-rw-r--r--	2021-11-01 05:53
omap-dma.h	9.79 KB	-rw-r--r--	2021-11-01 05:53
omap-gpmc.h	2.64 KB	-rw-r--r--	2021-11-01 05:53
omap-iommu.h	880 B	-rw-r--r--	2021-11-01 05:53
omap-mailbox.h	689 B	-rw-r--r--	2021-11-01 05:53
omapfb.h	576 B	-rw-r--r--	2021-11-01 05:53
once.h	2.8 KB	-rw-r--r--	2026-06-20 00:54
once_lite.h	925 B	-rw-r--r--	2026-06-20 00:54
oom.h	3.26 KB	-rw-r--r--	2021-11-01 05:53
openvswitch.h	403 B	-rw-r--r--	2021-11-01 05:53
osq_lock.h	1.04 KB	-rw-r--r--	2021-11-01 05:53
overflow.h	7.82 KB	-rw-r--r--	2026-06-20 00:54
packing.h	1.76 KB	-rw-r--r--	2021-11-01 05:53
padata.h	5.96 KB	-rw-r--r--	2026-06-20 00:54
page-flags-layout.h	3.21 KB	-rw-r--r--	2021-11-01 05:53
page-flags.h	28 KB	-rw-r--r--	2021-11-01 05:53
page-isolation.h	1.64 KB	-rw-r--r--	2021-11-01 05:53
page_counter.h	2.3 KB	-rw-r--r--	2021-11-01 05:53
page_ext.h	1.83 KB	-rw-r--r--	2021-11-01 05:53
page_idle.h	2.61 KB	-rw-r--r--	2021-11-01 05:53
page_owner.h	2.31 KB	-rw-r--r--	2021-11-01 05:53
page_ref.h	4.95 KB	-rw-r--r--	2021-11-01 05:53
page_reporting.h	895 B	-rw-r--r--	2021-11-01 05:53
pageblock-flags.h	2.31 KB	-rw-r--r--	2021-11-01 05:53
pagemap.h	30.5 KB	-rw-r--r--	2026-06-20 00:54
pagevec.h	2.04 KB	-rw-r--r--	2021-11-01 05:53
pagewalk.h	4.22 KB	-rw-r--r--	2026-06-20 00:54
panic.h	2.59 KB	-rw-r--r--	2026-06-20 00:54
panic_notifier.h	296 B	-rw-r--r--	2021-11-01 05:53
parman.h	2.87 KB	-rw-r--r--	2021-11-01 05:53
parport.h	19.09 KB	-rw-r--r--	2021-11-01 05:53
parport_pc.h	6.56 KB	-rw-r--r--	2021-11-01 05:53
parser.h	1.17 KB	-rw-r--r--	2021-11-01 05:53
part_stat.h	2.38 KB	-rw-r--r--	2026-06-20 00:54
pata_arasan_cf_data.h	1.22 KB	-rw-r--r--	2021-11-01 05:53
patchkey.h	757 B	-rw-r--r--	2021-11-01 05:53
path.h	572 B	-rw-r--r--	2021-11-01 05:53
pch_dma.h	408 B	-rw-r--r--	2021-11-01 05:53
pci-acpi.h	3.85 KB	-rw-r--r--	2021-11-01 05:53
pci-ats.h	1.76 KB	-rw-r--r--	2021-11-01 05:53
pci-dma-compat.h	3.66 KB	-rw-r--r--	2021-11-01 05:53
pci-ecam.h	3.2 KB	-rw-r--r--	2021-11-01 05:53
pci-ep-cfs.h	956 B	-rw-r--r--	2021-11-01 05:53
pci-epc.h	9.47 KB	-rw-r--r--	2021-11-01 05:53
pci-epf.h	7.06 KB	-rw-r--r--	2021-11-01 05:53
pci-p2pdma.h	3.95 KB	-rw-r--r--	2021-11-01 05:53
pci.h	90.67 KB	-rw-r--r--	2026-06-20 00:54
pci_hotplug.h	4.35 KB	-rw-r--r--	2021-11-01 05:53
pci_ids.h	121.23 KB	-rw-r--r--	2026-06-20 00:54
pcs-lynx.h	425 B	-rw-r--r--	2021-11-01 05:53
pda_power.h	1005 B	-rw-r--r--	2021-11-01 05:53
pe.h	16.17 KB	-rw-r--r--	2021-11-01 05:53
percpu-defs.h	18.12 KB	-rw-r--r--	2021-11-01 05:53
percpu-refcount.h	10.84 KB	-rw-r--r--	2021-11-01 05:53
percpu-rwsem.h	4.16 KB	-rw-r--r--	2021-11-01 05:53
percpu.h	4.74 KB	-rw-r--r--	2026-06-20 00:54
percpu_counter.h	5.48 KB	-rw-r--r--	2026-06-20 00:54
perf_event.h	47.23 KB	-rw-r--r--	2026-06-20 00:54
perf_regs.h	1.05 KB	-rw-r--r--	2021-11-01 05:53
personality.h	393 B	-rw-r--r--	2021-11-01 05:53
pfn.h	666 B	-rw-r--r--	2021-11-01 05:53
pfn_t.h	3.21 KB	-rw-r--r--	2021-11-01 05:53
pgalloc.h	948 B	-rw-r--r--	2026-06-20 00:54
pgtable.h	44.43 KB	-rw-r--r--	2026-06-20 00:54
phonet.h	537 B	-rw-r--r--	2021-11-01 05:53
phy.h	58.08 KB	-rw-r--r--	2026-06-20 00:54
phy_fixed.h	1.77 KB	-rw-r--r--	2021-11-01 05:53
phy_led_triggers.h	1.01 KB	-rw-r--r--	2021-11-01 05:53
phylink.h	19.47 KB	-rw-r--r--	2026-06-20 00:54
pid.h	6.37 KB	-rw-r--r--	2026-06-20 00:54
pid_namespace.h	2.08 KB	-rw-r--r--	2021-11-01 05:53
pim.h	2.67 KB	-rw-r--r--	2021-11-01 05:53
pipe_fs_i.h	9.21 KB	-rw-r--r--	2026-06-20 00:54
pkeys.h	990 B	-rw-r--r--	2021-11-01 05:53
pktcdvd.h	5.87 KB	-rw-r--r--	2021-11-01 05:53
pl320-ipc.h	209 B	-rw-r--r--	2021-11-01 05:53
platform_device.h	12.77 KB	-rw-r--r--	2026-06-20 00:54
platform_profile.h	1.12 KB	-rw-r--r--	2021-11-01 05:53
pldmfw.h	4.76 KB	-rw-r--r--	2021-11-01 05:53
plist.h	8.66 KB	-rw-r--r--	2021-11-01 05:53
pm-trace.h	940 B	-rw-r--r--	2021-11-01 05:53
pm.h	34.87 KB	-rw-r--r--	2026-06-20 00:54
pm_clock.h	2.58 KB	-rw-r--r--	2021-11-01 05:53
pm_domain.h	13.18 KB	-rw-r--r--	2021-11-01 05:53
pm_opp.h	15.1 KB	-rw-r--r--	2021-11-01 05:53
pm_qos.h	10.41 KB	-rw-r--r--	2021-11-01 05:53
pm_runtime.h	19.69 KB	-rw-r--r--	2026-06-20 00:54
pm_wakeirq.h	1.48 KB	-rw-r--r--	2026-06-20 00:54
pm_wakeup.h	6.28 KB	-rw-r--r--	2021-11-01 05:53
pmbus.h	2.48 KB	-rw-r--r--	2021-11-01 05:53
pmu.h	2.44 KB	-rw-r--r--	2021-11-01 05:53
pnfs_osd_xdr.h	9.27 KB	-rw-r--r--	2021-11-01 05:53
pnp.h	14.9 KB	-rw-r--r--	2021-11-01 05:53
poison.h	2.48 KB	-rw-r--r--	2021-11-01 05:53
poll.h	4.27 KB	-rw-r--r--	2026-06-20 00:54
posix-clock.h	4.7 KB	-rw-r--r--	2026-06-20 00:54
posix-timers.h	7.21 KB	-rw-r--r--	2026-06-20 00:54
posix_acl.h	3.27 KB	-rw-r--r--	2021-11-01 05:53
posix_acl_xattr.h	1.86 KB	-rw-r--r--	2026-06-20 00:54
power_supply.h	17.8 KB	-rw-r--r--	2026-06-20 00:54
powercap.h	11.98 KB	-rw-r--r--	2021-11-01 05:53
ppp-comp.h	2.95 KB	-rw-r--r--	2021-11-01 05:53
ppp_channel.h	2.99 KB	-rw-r--r--	2021-11-01 05:53
ppp_defs.h	305 B	-rw-r--r--	2021-11-01 05:53
pps_kernel.h	2.94 KB	-rw-r--r--	2026-06-20 00:54
pr.h	566 B	-rw-r--r--	2021-11-01 05:53
prandom.h	3.38 KB	-rw-r--r--	2026-06-20 00:54
preempt.h	14.7 KB	-rw-r--r--	2026-06-20 00:54
prefetch.h	1.7 KB	-rw-r--r--	2021-11-01 05:53
prime_numbers.h	1.35 KB	-rw-r--r--	2021-11-01 05:53
printk.h	22.19 KB	-rw-r--r--	2026-06-20 00:54
prmt.h	143 B	-rw-r--r--	2021-11-01 05:53
proc_fs.h	8.6 KB	-rw-r--r--	2026-06-20 00:54
proc_ns.h	2.57 KB	-rw-r--r--	2021-11-01 05:53
processor.h	1.84 KB	-rw-r--r--	2021-11-01 05:53
profile.h	2.62 KB	-rw-r--r--	2026-06-20 00:54
projid.h	2.22 KB	-rw-r--r--	2021-11-01 05:53
property.h	17.65 KB	-rw-r--r--	2026-06-20 00:54
pruss_driver.h	1.27 KB	-rw-r--r--	2021-11-01 05:53
psci.h	1.52 KB	-rw-r--r--	2021-11-01 05:53
pseudo_fs.h	355 B	-rw-r--r--	2021-11-01 05:53
psi.h	1.56 KB	-rw-r--r--	2026-06-20 00:54
psi_types.h	4.31 KB	-rw-r--r--	2026-06-20 00:54
psp-sev.h	17.76 KB	-rw-r--r--	2021-11-01 05:53
psp-tee.h	2.65 KB	-rw-r--r--	2021-11-01 05:53
pstore.h	7.63 KB	-rw-r--r--	2026-06-20 00:54
pstore_blk.h	1.53 KB	-rw-r--r--	2021-11-01 05:53
pstore_ram.h	3.82 KB	-rw-r--r--	2021-11-01 05:53
pstore_zone.h	2.28 KB	-rw-r--r--	2021-11-01 05:53
ptdump.h	567 B	-rw-r--r--	2021-11-01 05:53
pti.h	240 B	-rw-r--r--	2021-11-01 05:53
ptp_classify.h	4.85 KB	-rw-r--r--	2026-06-20 00:54
ptp_clock_kernel.h	12.2 KB	-rw-r--r--	2026-06-20 00:54
ptp_kvm.h	460 B	-rw-r--r--	2026-06-20 00:54
ptp_pch.h	623 B	-rw-r--r--	2021-11-01 05:53
ptr_ring.h	16.29 KB	-rw-r--r--	2021-11-01 05:53
ptrace.h	14.65 KB	-rw-r--r--	2026-06-20 00:54
purgatory.h	590 B	-rw-r--r--	2021-11-01 05:53
pvclock_gtod.h	548 B	-rw-r--r--	2021-11-01 05:53
pwm.h	16.46 KB	-rw-r--r--	2026-06-20 00:54
pwm_backlight.h	722 B	-rw-r--r--	2021-11-01 05:53
pxa168_eth.h	728 B	-rw-r--r--	2021-11-01 05:53
pxa2xx_ssp.h	11.13 KB	-rw-r--r--	2021-11-01 05:53
qcom-geni-se.h	13.74 KB	-rw-r--r--	2021-11-01 05:53
qcom_scm.h	3.81 KB	-rw-r--r--	2021-11-01 05:53
qnx6_fs.h	3.27 KB	-rw-r--r--	2021-11-01 05:53
quota.h	18.77 KB	-rw-r--r--	2026-06-20 00:54
quotaops.h	10.28 KB	-rw-r--r--	2026-06-20 00:54
radix-tree.h	15.63 KB	-rw-r--r--	2026-06-20 00:54
raid_class.h	2 KB	-rw-r--r--	2026-06-20 00:54
ramfs.h	746 B	-rw-r--r--	2026-06-20 00:54
random.h	3.98 KB	-rw-r--r--	2026-06-20 00:54
randomize_kstack.h	2.46 KB	-rw-r--r--	2026-06-20 00:54
range.h	775 B	-rw-r--r--	2021-11-01 05:53
ras.h	1.02 KB	-rw-r--r--	2021-11-01 05:53
ratelimit.h	1.72 KB	-rw-r--r--	2021-11-01 05:53
ratelimit_types.h	1.33 KB	-rw-r--r--	2026-06-20 00:54
rational.h	639 B	-rw-r--r--	2021-11-01 05:53
rbtree.h	8.93 KB	-rw-r--r--	2021-11-01 05:53
rbtree_augmented.h	9.53 KB	-rw-r--r--	2021-11-01 05:53
rbtree_latch.h	6.66 KB	-rw-r--r--	2026-06-20 00:54
rbtree_types.h	946 B	-rw-r--r--	2021-11-01 05:53
rcu_node_tree.h	3.73 KB	-rw-r--r--	2021-11-01 05:53
rcu_segcblist.h	10.03 KB	-rw-r--r--	2021-11-01 05:53
rcu_sync.h	1.46 KB	-rw-r--r--	2021-11-01 05:53
rculist.h	28.56 KB	-rw-r--r--	2021-11-01 05:53
rculist_bl.h	3.29 KB	-rw-r--r--	2021-11-01 05:53
rculist_nulls.h	8.68 KB	-rw-r--r--	2026-06-20 00:54
rcupdate.h	38.69 KB	-rw-r--r--	2026-06-20 00:54
rcupdate_trace.h	3.08 KB	-rw-r--r--	2021-11-01 05:53
rcupdate_wait.h	1.73 KB	-rw-r--r--	2021-11-01 05:53
rcutiny.h	3.32 KB	-rw-r--r--	2021-11-01 05:53
rcutree.h	2.34 KB	-rw-r--r--	2026-06-20 00:54
rcuwait.h	1.84 KB	-rw-r--r--	2021-11-01 05:53
reboot-mode.h	600 B	-rw-r--r--	2021-11-01 05:53
reboot.h	2.18 KB	-rw-r--r--	2021-11-01 05:53
reciprocal_div.h	3.28 KB	-rw-r--r--	2021-11-01 05:53
refcount.h	12.02 KB	-rw-r--r--	2021-11-01 05:53
regmap.h	63.97 KB	-rw-r--r--	2026-06-20 00:54
regset.h	11.35 KB	-rw-r--r--	2021-11-01 05:53
relay.h	8.47 KB	-rw-r--r--	2021-11-01 05:53
remoteproc.h	24.77 KB	-rw-r--r--	2021-11-01 05:53
resctrl.h	6.5 KB	-rw-r--r--	2021-11-01 05:53
reset-controller.h	3.57 KB	-rw-r--r--	2021-11-01 05:53
reset.h	30.24 KB	-rw-r--r--	2026-06-20 00:54
resource.h	339 B	-rw-r--r--	2021-11-01 05:53
resource_ext.h	2.08 KB	-rw-r--r--	2021-11-01 05:53
restart_block.h	1.11 KB	-rw-r--r--	2021-11-01 05:53
rfkill.h	10.52 KB	-rw-r--r--	2021-11-01 05:53
rhashtable-types.h	3.45 KB	-rw-r--r--	2021-11-01 05:53
rhashtable.h	37.59 KB	-rw-r--r--	2021-11-01 05:53
ring_buffer.h	7.56 KB	-rw-r--r--	2026-06-20 00:54
rio.h	19.02 KB	-rw-r--r--	2021-11-01 05:53
rio_drv.h	14.32 KB	-rw-r--r--	2021-11-01 05:53
rio_ids.h	1.08 KB	-rw-r--r--	2021-11-01 05:53
rio_regs.h	19.07 KB	-rw-r--r--	2021-11-01 05:53
rmap.h	9.13 KB	-rw-r--r--	2026-06-20 00:54
rmi.h	12.04 KB	-rw-r--r--	2021-11-01 05:53
rndis.h	16.86 KB	-rw-r--r--	2021-11-01 05:53
rodata_test.h	394 B	-rw-r--r--	2021-11-01 05:53
root_dev.h	619 B	-rw-r--r--	2021-11-01 05:53
rpmsg.h	8.77 KB	-rw-r--r--	2026-06-20 00:54
rslib.h	3.67 KB	-rw-r--r--	2021-11-01 05:53
rtc.h	8.65 KB	-rw-r--r--	2021-11-01 05:53
rtmutex.h	2.97 KB	-rw-r--r--	2021-11-01 05:53
rtnetlink.h	4.46 KB	-rw-r--r--	2021-11-01 05:53
rtsx_common.h	890 B	-rw-r--r--	2021-11-01 05:53
rtsx_pci.h	39.82 KB	-rw-r--r--	2026-06-20 00:54
rtsx_usb.h	15.38 KB	-rw-r--r--	2026-06-20 00:54
rwbase_rt.h	876 B	-rw-r--r--	2021-11-01 05:53
rwlock.h	4.55 KB	-rw-r--r--	2021-11-01 05:53
rwlock_api_smp.h	7.65 KB	-rw-r--r--	2021-11-01 05:53
rwlock_rt.h	2.98 KB	-rw-r--r--	2021-11-01 05:53
rwlock_types.h	1.77 KB	-rw-r--r--	2021-11-01 05:53
rwsem.h	7.63 KB	-rw-r--r--	2026-06-20 00:54
s3c_adc_battery.h	923 B	-rw-r--r--	2021-11-01 05:53
sbitmap.h	16.9 KB	-rw-r--r--	2021-11-01 05:53
scatterlist.h	17.56 KB	-rw-r--r--	2021-11-01 05:53
scc.h	2.84 KB	-rw-r--r--	2021-11-01 05:53
sched.h	64.73 KB	-rw-r--r--	2026-06-20 00:54
sched_clock.h	1.44 KB	-rw-r--r--	2021-11-01 05:53
scmi_protocol.h	26.06 KB	-rw-r--r--	2026-06-20 00:54
scpi_protocol.h	2.67 KB	-rw-r--r--	2021-11-01 05:53
screen_info.h	191 B	-rw-r--r--	2021-11-01 05:53
scs.h	1.83 KB	-rw-r--r--	2021-11-01 05:53
sctp.h	22.88 KB	-rw-r--r--	2021-11-01 05:53
scx200.h	1.82 KB	-rw-r--r--	2021-11-01 05:53
scx200_gpio.h	2.38 KB	-rw-r--r--	2021-11-01 05:53
sdb.h	4.17 KB	-rw-r--r--	2021-11-01 05:53
seccomp.h	3.45 KB	-rw-r--r--	2026-06-20 00:54
secretmem.h	1.14 KB	-rw-r--r--	2026-06-20 00:54
securebits.h	239 B	-rw-r--r--	2021-11-01 05:53
security.h	58.92 KB	-rw-r--r--	2026-06-20 00:54
sed-opal.h	1.66 KB	-rw-r--r--	2021-11-01 05:53
seg6.h	121 B	-rw-r--r--	2021-11-01 05:53
seg6_genl.h	136 B	-rw-r--r--	2021-11-01 05:53
seg6_hmac.h	136 B	-rw-r--r--	2021-11-01 05:53
seg6_iptunnel.h	148 B	-rw-r--r--	2021-11-01 05:53
seg6_local.h	100 B	-rw-r--r--	2021-11-01 05:53
selection.h	1.81 KB	-rw-r--r--	2021-11-01 05:53
sem.h	599 B	-rw-r--r--	2021-11-01 05:53
semaphore.h	1.35 KB	-rw-r--r--	2021-11-01 05:53
seq_buf.h	3.94 KB	-rw-r--r--	2021-11-01 05:53
seq_file.h	9 KB	-rw-r--r--	2026-06-20 00:54
seq_file_net.h	730 B	-rw-r--r--	2021-11-01 05:53
seqlock.h	39.51 KB	-rw-r--r--	2026-06-20 00:54
seqno-fence.h	3.57 KB	-rw-r--r--	2021-11-01 05:53
serdev.h	9.82 KB	-rw-r--r--	2021-11-01 05:53
serial.h	630 B	-rw-r--r--	2021-11-01 05:53
serial_8250.h	6.57 KB	-rw-r--r--	2026-06-20 00:54
serial_bcm63xx.h	4.73 KB	-rw-r--r--	2021-11-01 05:53
serial_core.h	20.46 KB	-rw-r--r--	2026-06-20 00:54
serial_max3100.h	1.19 KB	-rw-r--r--	2021-11-01 05:53
serial_s3c.h	9.42 KB	-rw-r--r--	2021-11-01 05:53
serial_sci.h	1.6 KB	-rw-r--r--	2021-11-01 05:53
serio.h	4.28 KB	-rw-r--r--	2021-11-01 05:53
set_memory.h	1.66 KB	-rw-r--r--	2021-11-01 05:53
sfp.h	15.87 KB	-rw-r--r--	2021-11-01 05:53
sh_clk.h	5.96 KB	-rw-r--r--	2021-11-01 05:53
sh_dma.h	3.47 KB	-rw-r--r--	2021-11-01 05:53
sh_eth.h	369 B	-rw-r--r--	2021-11-01 05:53
sh_intc.h	3.59 KB	-rw-r--r--	2026-06-20 00:54
sh_timer.h	172 B	-rw-r--r--	2021-11-01 05:53
shdma-base.h	4.27 KB	-rw-r--r--	2026-06-20 00:54
shm.h	968 B	-rw-r--r--	2021-11-01 05:53
shmem_fs.h	5.81 KB	-rw-r--r--	2021-11-01 05:53
shrinker.h	3.25 KB	-rw-r--r--	2021-11-01 05:53
signal.h	13.75 KB	-rw-r--r--	2026-06-20 00:54
signal_types.h	1.68 KB	-rw-r--r--	2026-06-20 00:54
signalfd.h	817 B	-rw-r--r--	2021-11-01 05:53
siox.h	2.26 KB	-rw-r--r--	2021-11-01 05:53
siphash.h	5.59 KB	-rw-r--r--	2026-06-20 00:54
sizes.h	1.27 KB	-rw-r--r--	2021-11-01 05:53
skb_array.h	5.18 KB	-rw-r--r--	2021-11-01 05:53
skbuff.h	137.84 KB	-rw-r--r--	2026-06-20 00:54
skmsg.h	13.44 KB	-rw-r--r--	2026-06-20 00:54
slab.h	23.74 KB	-rw-r--r--	2026-06-20 00:54
slab_def.h	3.02 KB	-rw-r--r--	2021-11-01 05:53
slimbus.h	6.93 KB	-rw-r--r--	2021-11-01 05:53
slub_def.h	6.22 KB	-rw-r--r--	2021-11-01 05:53
sm501-regs.h	11.62 KB	-rw-r--r--	2021-11-01 05:53
sm501.h	4.02 KB	-rw-r--r--	2021-11-01 05:53
smc911x.h	294 B	-rw-r--r--	2021-11-01 05:53
smc91x.h	1.57 KB	-rw-r--r--	2021-11-01 05:53
smp.h	7.63 KB	-rw-r--r--	2021-11-01 05:53
smp_types.h	1.35 KB	-rw-r--r--	2021-11-01 05:53
smpboot.h	1.68 KB	-rw-r--r--	2021-11-01 05:53
smsc911x.h	1.63 KB	-rw-r--r--	2021-11-01 05:53
smscphy.h	1.25 KB	-rw-r--r--	2021-11-01 05:53
sock_diag.h	2.31 KB	-rw-r--r--	2021-11-01 05:53
socket.h	15.1 KB	-rw-r--r--	2026-06-20 00:54
sockptr.h	2.36 KB	-rw-r--r--	2026-06-20 00:54
sonet.h	469 B	-rw-r--r--	2021-11-01 05:53
sony-laptop.h	1.41 KB	-rw-r--r--	2021-11-01 05:53
sonypi.h	1.71 KB	-rw-r--r--	2021-11-01 05:53
sort.h	346 B	-rw-r--r--	2021-11-01 05:53
sound.h	685 B	-rw-r--r--	2021-11-01 05:53
soundcard.h	1.59 KB	-rw-r--r--	2021-11-01 05:53
spinlock.h	15.08 KB	-rw-r--r--	2026-06-20 00:54
spinlock_api_smp.h	5.47 KB	-rw-r--r--	2021-11-01 05:53
spinlock_api_up.h	3.31 KB	-rw-r--r--	2021-11-01 05:53
spinlock_rt.h	4.11 KB	-rw-r--r--	2021-11-01 05:53
spinlock_types.h	1.78 KB	-rw-r--r--	2021-11-01 05:53
spinlock_types_raw.h	1.69 KB	-rw-r--r--	2021-11-01 05:53
spinlock_types_up.h	726 B	-rw-r--r--	2021-11-01 05:53
spinlock_up.h	2.16 KB	-rw-r--r--	2021-11-01 05:53
splice.h	3.31 KB	-rw-r--r--	2026-06-20 00:54
spmi.h	5.59 KB	-rw-r--r--	2021-11-01 05:53
sram.h	844 B	-rw-r--r--	2021-11-01 05:53
srcu.h	7.07 KB	-rw-r--r--	2026-06-20 00:54
srcutiny.h	2.75 KB	-rw-r--r--	2021-11-01 05:53
srcutree.h	4.8 KB	-rw-r--r--	2021-11-01 05:53
ssbi.h	726 B	-rw-r--r--	2021-11-01 05:53
stackdepot.h	686 B	-rw-r--r--	2026-06-20 00:54
stackleak.h	902 B	-rw-r--r--	2021-11-01 05:53
stackprotector.h	361 B	-rw-r--r--	2021-11-01 05:53
stacktrace.h	3.97 KB	-rw-r--r--	2026-06-20 00:54
start_kernel.h	415 B	-rw-r--r--	2021-11-01 05:53
stat.h	1.33 KB	-rw-r--r--	2021-11-01 05:53
statfs.h	1.78 KB	-rw-r--r--	2021-11-01 05:53
static_call.h	10.25 KB	-rw-r--r--	2026-06-20 00:54
static_call_types.h	2.74 KB	-rw-r--r--	2021-11-01 05:53
static_key.h	30 B	-rw-r--r--	2021-11-01 05:53
stdarg.h	313 B	-rw-r--r--	2021-11-01 05:53
stddef.h	3.2 KB	-rw-r--r--	2026-06-20 00:54
stm.h	4.34 KB	-rw-r--r--	2021-11-01 05:53
stmmac.h	6.86 KB	-rw-r--r--	2026-06-20 00:54
stmp3xxx_rtc_wdt.h	331 B	-rw-r--r--	2021-11-01 05:53
stmp_device.h	412 B	-rw-r--r--	2021-11-01 05:53
stop_machine.h	4.41 KB	-rw-r--r--	2021-11-01 05:53
string.h	9.75 KB	-rw-r--r--	2026-06-20 00:54
string_helpers.h	2.69 KB	-rw-r--r--	2021-11-01 05:53
stringhash.h	2.65 KB	-rw-r--r--	2021-11-01 05:53
stringify.h	341 B	-rw-r--r--	2021-11-01 05:53
sungem_phy.h	3.94 KB	-rw-r--r--	2021-11-01 05:53
sunserialcore.h	1.08 KB	-rw-r--r--	2021-11-01 05:53
sunxi-rsb.h	2.89 KB	-rw-r--r--	2021-11-01 05:53
superhyway.h	2.81 KB	-rw-r--r--	2021-11-01 05:53
surface_acpi_notify.h	1.07 KB	-rw-r--r--	2021-11-01 05:53
suspend.h	20.02 KB	-rw-r--r--	2026-06-20 00:54
svga.h	3.75 KB	-rw-r--r--	2021-11-01 05:53
sw842.h	328 B	-rw-r--r--	2021-11-01 05:53
swab.h	569 B	-rw-r--r--	2021-11-01 05:53
swait.h	9.45 KB	-rw-r--r--	2021-11-01 05:53
swap.h	23.43 KB	-rw-r--r--	2026-06-20 00:54
swap_cgroup.h	971 B	-rw-r--r--	2021-11-01 05:53
swap_slots.h	841 B	-rw-r--r--	2021-11-01 05:53
swapfile.h	556 B	-rw-r--r--	2021-11-01 05:53
swapops.h	9.61 KB	-rw-r--r--	2021-11-01 05:53
swiotlb.h	5.36 KB	-rw-r--r--	2026-06-20 00:54
switchtec.h	10.9 KB	-rw-r--r--	2021-11-01 05:53
sxgbe_platform.h	1.23 KB	-rw-r--r--	2021-11-01 05:53
sync_core.h	581 B	-rw-r--r--	2021-11-01 05:53
sync_file.h	1.57 KB	-rw-r--r--	2021-11-01 05:53
synclink.h	989 B	-rw-r--r--	2021-11-01 05:53
sys.h	960 B	-rw-r--r--	2021-11-01 05:53
sys_soc.h	1.26 KB	-rw-r--r--	2021-11-01 05:53
syscall_user_dispatch.h	930 B	-rw-r--r--	2021-11-01 05:53
syscalls.h	55.56 KB	-rw-r--r--	2026-06-20 00:54
syscore_ops.h	633 B	-rw-r--r--	2021-11-01 05:53
sysctl.h	8.59 KB	-rw-r--r--	2026-06-20 00:54
sysfb.h	2.67 KB	-rw-r--r--	2026-06-20 00:54
sysfs.h	17.64 KB	-rw-r--r--	2021-11-01 05:53
syslog.h	1.24 KB	-rw-r--r--	2021-11-01 05:53
sysrq.h	1.96 KB	-rw-r--r--	2021-11-01 05:53
sysv_fs.h	9.03 KB	-rw-r--r--	2021-11-01 05:53
t10-pi.h	1.5 KB	-rw-r--r--	2021-11-01 05:53
task_io_accounting.h	1.13 KB	-rw-r--r--	2021-11-01 05:53
task_io_accounting_ops.h	2.55 KB	-rw-r--r--	2021-11-01 05:53
task_work.h	934 B	-rw-r--r--	2026-06-20 00:54
taskstats_kern.h	957 B	-rw-r--r--	2021-11-01 05:53
tboot.h	3.33 KB	-rw-r--r--	2021-11-01 05:53
tc.h	3.45 KB	-rw-r--r--	2021-11-01 05:53
tca6416_keypad.h	683 B	-rw-r--r--	2026-06-20 00:54
tcp.h	17.14 KB	-rw-r--r--	2026-06-20 00:54
tee_drv.h	18.35 KB	-rw-r--r--	2026-06-20 00:54
textsearch.h	4.75 KB	-rw-r--r--	2026-06-20 00:54
textsearch_fsm.h	1.19 KB	-rw-r--r--	2021-11-01 05:53
tfrc.h	1.68 KB	-rw-r--r--	2021-11-01 05:53
thermal.h	15.44 KB	-rw-r--r--	2026-06-20 00:54
thread_info.h	6.89 KB	-rw-r--r--	2026-06-20 00:54
threads.h	1.28 KB	-rw-r--r--	2021-11-01 05:53
thunderbolt.h	20.78 KB	-rw-r--r--	2021-11-01 05:53
ti-emif-sram.h	5.15 KB	-rw-r--r--	2021-11-01 05:53
ti_wilink_st.h	13.46 KB	-rw-r--r--	2021-11-01 05:53
tick.h	10.05 KB	-rw-r--r--	2026-06-20 00:54
tifm.h	4.66 KB	-rw-r--r--	2021-11-01 05:53
timb_dma.h	1.17 KB	-rw-r--r--	2021-11-01 05:53
timb_gpio.h	717 B	-rw-r--r--	2021-11-01 05:53
time.h	3.14 KB	-rw-r--r--	2021-11-01 05:53
time32.h	1.75 KB	-rw-r--r--	2021-11-01 05:53
time64.h	4.49 KB	-rw-r--r--	2021-11-01 05:53
time_namespace.h	3.82 KB	-rw-r--r--	2021-11-01 05:53
timecounter.h	4.14 KB	-rw-r--r--	2021-11-01 05:53
timekeeper_internal.h	5.33 KB	-rw-r--r--	2021-11-01 05:53
timekeeping.h	7.61 KB	-rw-r--r--	2021-11-01 05:53
timer.h	7.9 KB	-rw-r--r--	2026-06-20 00:54
timerfd.h	508 B	-rw-r--r--	2021-11-01 05:53
timeriomem-rng.h	432 B	-rw-r--r--	2021-11-01 05:53
timerqueue.h	1.4 KB	-rw-r--r--	2026-06-20 00:54
timex.h	6.67 KB	-rw-r--r--	2026-06-20 00:54
tnum.h	3.39 KB	-rw-r--r--	2021-11-01 05:53
topology.h	5.25 KB	-rw-r--r--	2021-11-01 05:53
torture.h	4.48 KB	-rw-r--r--	2026-06-20 00:54
toshiba.h	460 B	-rw-r--r--	2021-11-01 05:53
tpm.h	11.07 KB	-rw-r--r--	2026-06-20 00:54
tpm_command.h	847 B	-rw-r--r--	2021-11-01 05:53
tpm_eventlog.h	6.53 KB	-rw-r--r--	2026-06-20 00:54
trace.h	2.72 KB	-rw-r--r--	2026-06-20 00:54
trace_clock.h	667 B	-rw-r--r--	2021-11-01 05:53
trace_events.h	27.68 KB	-rw-r--r--	2026-06-20 00:54
trace_recursion.h	5.49 KB	-rw-r--r--	2026-06-20 00:54
trace_seq.h	3.94 KB	-rw-r--r--	2026-06-20 00:54
tracefs.h	1018 B	-rw-r--r--	2021-11-01 05:53
tracehook.h	7.97 KB	-rw-r--r--	2021-11-01 05:53
tracepoint-defs.h	2.34 KB	-rw-r--r--	2021-11-01 05:53
tracepoint.h	18 KB	-rw-r--r--	2026-06-20 00:54
transport_class.h	2.58 KB	-rw-r--r--	2026-06-20 00:54
ts-nbus.h	532 B	-rw-r--r--	2021-11-01 05:53
tsacct_kern.h	1.2 KB	-rw-r--r--	2021-11-01 05:53
tty.h	14.52 KB	-rw-r--r--	2021-11-01 05:53
tty_buffer.h	1.28 KB	-rw-r--r--	2021-11-01 05:53
tty_driver.h	15.69 KB	-rw-r--r--	2021-11-01 05:53
tty_flip.h	1.69 KB	-rw-r--r--	2026-06-20 00:54
tty_ldisc.h	8.46 KB	-rw-r--r--	2021-11-01 05:53
tty_port.h	7.24 KB	-rw-r--r--	2021-11-01 05:53
typecheck.h	782 B	-rw-r--r--	2021-11-01 05:53
types.h	5.68 KB	-rw-r--r--	2026-06-20 00:54
u64_stats_sync.h	6.41 KB	-rw-r--r--	2026-06-20 00:54
uacce.h	3.79 KB	-rw-r--r--	2026-06-20 00:54
uaccess.h	13.06 KB	-rw-r--r--	2026-06-20 00:54
ucb1400.h	4.12 KB	-rw-r--r--	2021-11-01 05:53
ucs2_string.h	662 B	-rw-r--r--	2021-11-01 05:53
udp.h	5.3 KB	-rw-r--r--	2026-06-20 00:54
uidgid.h	4.07 KB	-rw-r--r--	2021-11-01 05:53
uio.h	9.1 KB	-rw-r--r--	2026-06-20 00:54
uio_driver.h	4.71 KB	-rw-r--r--	2021-11-01 05:53
umh.h	1.79 KB	-rw-r--r--	2021-11-01 05:53
unicode.h	1.02 KB	-rw-r--r--	2021-11-01 05:53
units.h	2.59 KB	-rw-r--r--	2021-11-01 05:53
uprobes.h	6 KB	-rw-r--r--	2021-11-01 05:53
usb.h	77.76 KB	-rw-r--r--	2026-06-20 00:54
usb_usual.h	3.58 KB	-rw-r--r--	2021-11-01 05:53
usbdevice_fs.h	2.18 KB	-rw-r--r--	2021-11-01 05:53
user-return-notifier.h	1.18 KB	-rw-r--r--	2021-11-01 05:53
user.h	22 B	-rw-r--r--	2021-11-01 05:53
user_namespace.h	6.03 KB	-rw-r--r--	2026-06-20 00:54
userfaultfd_k.h	6.44 KB	-rw-r--r--	2021-11-01 05:53
usermode_driver.h	515 B	-rw-r--r--	2021-11-01 05:53
util_macros.h	2.49 KB	-rw-r--r--	2026-06-20 00:54
uts.h	388 B	-rw-r--r--	2021-11-01 05:53
utsname.h	1.78 KB	-rw-r--r--	2021-11-01 05:53
uuid.h	2.34 KB	-rw-r--r--	2021-11-01 05:53
vbox_utils.h	1.75 KB	-rw-r--r--	2021-11-01 05:53
vdpa.h	14.38 KB	-rw-r--r--	2026-06-20 00:54
verification.h	1.77 KB	-rw-r--r--	2021-11-01 05:53
vermagic.h	1.28 KB	-rw-r--r--	2021-11-01 05:53
vexpress.h	297 B	-rw-r--r--	2021-11-01 05:53
vfio.h	8.3 KB	-rw-r--r--	2026-06-20 00:54
vfio_pci_core.h	8.07 KB	-rw-r--r--	2026-06-20 00:54
vfs.h	116 B	-rw-r--r--	2021-11-01 05:53
vga_switcheroo.h	8.62 KB	-rw-r--r--	2021-11-01 05:53
vgaarb.h	3.88 KB	-rw-r--r--	2021-11-01 05:53
vhost_iotlb.h	1.34 KB	-rw-r--r--	2021-11-01 05:53
via-core.h	6.57 KB	-rw-r--r--	2021-11-01 05:53
via-gpio.h	310 B	-rw-r--r--	2021-11-01 05:53
via.h	932 B	-rw-r--r--	2021-11-01 05:53
via_i2c.h	844 B	-rw-r--r--	2021-11-01 05:53
videodev2.h	2.7 KB	-rw-r--r--	2021-11-01 05:53
virtio.h	6.7 KB	-rw-r--r--	2026-06-20 00:54
virtio_byteorder.h	1.46 KB	-rw-r--r--	2021-11-01 05:53
virtio_caif.h	513 B	-rw-r--r--	2021-11-01 05:53
virtio_config.h	16.25 KB	-rw-r--r--	2026-06-20 00:54
virtio_console.h	1.93 KB	-rw-r--r--	2021-11-01 05:53
virtio_dma_buf.h	1.12 KB	-rw-r--r--	2021-11-01 05:53
virtio_net.h	6.01 KB	-rw-r--r--	2026-06-20 00:54
virtio_pci_modern.h	3.25 KB	-rw-r--r--	2021-11-01 05:53
virtio_ring.h	2.95 KB	-rw-r--r--	2021-11-01 05:53
virtio_vsock.h	4.79 KB	-rw-r--r--	2021-11-01 05:53
visorbus.h	12.23 KB	-rw-r--r--	2021-11-01 05:53
vlynq.h	3.22 KB	-rw-r--r--	2021-11-01 05:53
vm_event_item.h	3.46 KB	-rw-r--r--	2021-11-01 05:53
vmacache.h	722 B	-rw-r--r--	2021-11-01 05:53
vmalloc.h	8.4 KB	-rw-r--r--	2026-06-20 00:54
vme.h	5.66 KB	-rw-r--r--	2021-11-01 05:53
vmpressure.h	1.68 KB	-rw-r--r--	2021-11-01 05:53
vmstat.h	14.79 KB	-rw-r--r--	2026-06-20 00:54
vmw_vmci_api.h	2.88 KB	-rw-r--r--	2021-11-01 05:53
vmw_vmci_defs.h	30.03 KB	-rw-r--r--	2026-06-20 00:54
vringh.h	8.62 KB	-rw-r--r--	2021-11-01 05:53
vsc.h	1.87 KB	-rw-r--r--	2026-06-20 00:54
vt.h	611 B	-rw-r--r--	2021-11-01 05:53
vt_buffer.h	1.49 KB	-rw-r--r--	2026-06-20 00:54
vt_kern.h	5.31 KB	-rw-r--r--	2021-11-01 05:53
vtime.h	4.6 KB	-rw-r--r--	2021-11-01 05:53
w1-gpio.h	493 B	-rw-r--r--	2021-11-01 05:53
w1.h	8.93 KB	-rw-r--r--	2021-11-01 05:53
wait.h	42.04 KB	-rw-r--r--	2026-06-20 00:54
wait_bit.h	11.2 KB	-rw-r--r--	2021-11-01 05:53
watch_queue.h	3.82 KB	-rw-r--r--	2026-06-20 00:54
watchdog.h	8.21 KB	-rw-r--r--	2021-11-01 05:53
win_minmax.h	832 B	-rw-r--r--	2021-11-01 05:53
wireless.h	1.57 KB	-rw-r--r--	2026-06-20 00:54
wkup_m3_ipc.h	1.75 KB	-rw-r--r--	2021-11-01 05:53
wl12xx.h	810 B	-rw-r--r--	2021-11-01 05:53
wm97xx.h	10.59 KB	-rw-r--r--	2021-11-01 05:53
wmi.h	1.56 KB	-rw-r--r--	2021-11-01 05:53
workqueue.h	22.44 KB	-rw-r--r--	2026-06-20 00:54
writeback.h	12.83 KB	-rw-r--r--	2021-11-01 05:53
ww_mutex.h	13.11 KB	-rw-r--r--	2021-11-01 05:53
wwan.h	5.13 KB	-rw-r--r--	2021-11-01 05:53
xarray.h	56.45 KB	-rw-r--r--	2026-06-20 00:54
xattr.h	3.88 KB	-rw-r--r--	2021-11-01 05:53
xxhash.h	8.27 KB	-rw-r--r--	2021-11-01 05:53
xz.h	11.16 KB	-rw-r--r--	2021-11-01 05:53
yam.h	2.18 KB	-rw-r--r--	2021-11-01 05:53
z2_battery.h	299 B	-rw-r--r--	2021-11-01 05:53
zconf.h	1.73 KB	-rw-r--r--	2021-11-01 05:53
zlib.h	28.11 KB	-rw-r--r--	2021-11-01 05:53
zorro.h	3.57 KB	-rw-r--r--	2021-11-01 05:53
zpool.h	3.24 KB	-rw-r--r--	2021-11-01 05:53
zsmalloc.h	1.63 KB	-rw-r--r--	2021-11-01 05:53
zstd.h	48.58 KB	-rw-r--r--	2021-11-01 05:53
zutil.h	2.73 KB	-rw-r--r--	2021-11-01 05:53

Rename

/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
 *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
 */
#ifndef __LINUX_CLK_PROVIDER_H
#define __LINUX_CLK_PROVIDER_H

#include <linux/of.h>
#include <linux/of_clk.h>

/*
 * flags used across common struct clk.  these flags should only affect the
 * top-level framework.  custom flags for dealing with hardware specifics
 * belong in struct clk_foo
 *
 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
 */
#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
				/* unused */
				/* unused */
#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE	BIT(12)
/* duty cycle call may be forwarded to the parent clock */
#define CLK_DUTY_CYCLE_PARENT	BIT(13)

struct clk;
struct clk_hw;
struct clk_core;
struct dentry;

/**
 * struct clk_rate_request - Structure encoding the clk constraints that
 * a clock user might require.
 *
 * @rate:		Requested clock rate. This field will be adjusted by
 *			clock drivers according to hardware capabilities.
 * @min_rate:		Minimum rate imposed by clk users.
 * @max_rate:		Maximum rate imposed by clk users.
 * @best_parent_rate:	The best parent rate a parent can provide to fulfill the
 *			requested constraints.
 * @best_parent_hw:	The most appropriate parent clock that fulfills the
 *			requested constraints.
 *
 */
struct clk_rate_request {
	unsigned long rate;
	unsigned long min_rate;
	unsigned long max_rate;
	unsigned long best_parent_rate;
	struct clk_hw *best_parent_hw;
};

/**
 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
 *
 * @num:	Numerator of the duty cycle ratio
 * @den:	Denominator of the duty cycle ratio
 */
struct clk_duty {
	unsigned int num;
	unsigned int den;
};

/**
 * struct clk_ops -  Callback operations for hardware clocks; these are to
 * be provided by the clock implementation, and will be called by drivers
 * through the clk_* api.
 *
 * @prepare:	Prepare the clock for enabling. This must not return until
 *		the clock is fully prepared, and it's safe to call clk_enable.
 *		This callback is intended to allow clock implementations to
 *		do any initialisation that may sleep. Called with
 *		prepare_lock held.
 *
 * @unprepare:	Release the clock from its prepared state. This will typically
 *		undo any work done in the @prepare callback. Called with
 *		prepare_lock held.
 *
 * @is_prepared: Queries the hardware to determine if the clock is prepared.
 *		This function is allowed to sleep. Optional, if this op is not
 *		set then the prepare count will be used.
 *
 * @unprepare_unused: Unprepare the clock atomically.  Only called from
 *		clk_disable_unused for prepare clocks with special needs.
 *		Called with prepare mutex held. This function may sleep.
 *
 * @enable:	Enable the clock atomically. This must not return until the
 *		clock is generating a valid clock signal, usable by consumer
 *		devices. Called with enable_lock held. This function must not
 *		sleep.
 *
 * @disable:	Disable the clock atomically. Called with enable_lock held.
 *		This function must not sleep.
 *
 * @is_enabled:	Queries the hardware to determine if the clock is enabled.
 *		This function must not sleep. Optional, if this op is not
 *		set then the enable count will be used.
 *
 * @disable_unused: Disable the clock atomically.  Only called from
 *		clk_disable_unused for gate clocks with special needs.
 *		Called with enable_lock held.  This function must not
 *		sleep.
 *
 * @save_context: Save the context of the clock in prepration for poweroff.
 *
 * @restore_context: Restore the context of the clock after a restoration
 *		of power.
 *
 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
 *		parent rate is an input parameter.  It is up to the caller to
 *		ensure that the prepare_mutex is held across this call.
 *		Returns the calculated rate.  Optional, but recommended - if
 *		this op is not set then clock rate will be initialized to 0.
 *
 * @round_rate:	Given a target rate as input, returns the closest rate actually
 *		supported by the clock. The parent rate is an input/output
 *		parameter.
 *
 * @determine_rate: Given a target rate as input, returns the closest rate
 *		actually supported by the clock, and optionally the parent clock
 *		that should be used to provide the clock rate.
 *
 * @set_parent:	Change the input source of this clock; for clocks with multiple
 *		possible parents specify a new parent by passing in the index
 *		as a u8 corresponding to the parent in either the .parent_names
 *		or .parents arrays.  This function in affect translates an
 *		array index into the value programmed into the hardware.
 *		Returns 0 on success, -EERROR otherwise.
 *
 * @get_parent:	Queries the hardware to determine the parent of a clock.  The
 *		return value is a u8 which specifies the index corresponding to
 *		the parent clock.  This index can be applied to either the
 *		.parent_names or .parents arrays.  In short, this function
 *		translates the parent value read from hardware into an array
 *		index.  Currently only called when the clock is initialized by
 *		__clk_init.  This callback is mandatory for clocks with
 *		multiple parents.  It is optional (and unnecessary) for clocks
 *		with 0 or 1 parents.
 *
 * @set_rate:	Change the rate of this clock. The requested rate is specified
 *		by the second argument, which should typically be the return
 *		of .round_rate call.  The third argument gives the parent rate
 *		which is likely helpful for most .set_rate implementation.
 *		Returns 0 on success, -EERROR otherwise.
 *
 * @set_rate_and_parent: Change the rate and the parent of this clock. The
 *		requested rate is specified by the second argument, which
 *		should typically be the return of .round_rate call.  The
 *		third argument gives the parent rate which is likely helpful
 *		for most .set_rate_and_parent implementation. The fourth
 *		argument gives the parent index. This callback is optional (and
 *		unnecessary) for clocks with 0 or 1 parents as well as
 *		for clocks that can tolerate switching the rate and the parent
 *		separately via calls to .set_parent and .set_rate.
 *		Returns 0 on success, -EERROR otherwise.
 *
 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
 *		is expressed in ppb (parts per billion). The parent accuracy is
 *		an input parameter.
 *		Returns the calculated accuracy.  Optional - if	this op is not
 *		set then clock accuracy will be initialized to parent accuracy
 *		or 0 (perfect clock) if clock has no parent.
 *
 * @get_phase:	Queries the hardware to get the current phase of a clock.
 *		Returned values are 0-359 degrees on success, negative
 *		error codes on failure.
 *
 * @set_phase:	Shift the phase this clock signal in degrees specified
 *		by the second argument. Valid values for degrees are
 *		0-359. Return 0 on success, otherwise -EERROR.
 *
 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
 *              of a clock. Returned values denominator cannot be 0 and must be
 *              superior or equal to the numerator.
 *
 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
 *              the numerator (2nd argurment) and denominator (3rd  argument).
 *              Argument must be a valid ratio (denominator > 0
 *              and >= numerator) Return 0 on success, otherwise -EERROR.
 *
 * @init:	Perform platform-specific initialization magic.
 *		This is not used by any of the basic clock types.
 *		This callback exist for HW which needs to perform some
 *		initialisation magic for CCF to get an accurate view of the
 *		clock. It may also be used dynamic resource allocation is
 *		required. It shall not used to deal with clock parameters,
 *		such as rate or parents.
 *		Returns 0 on success, -EERROR otherwise.
 *
 * @terminate:  Free any resource allocated by init.
 *
 * @debug_init:	Set up type-specific debugfs entries for this clock.  This
 *		is called once, after the debugfs directory entry for this
 *		clock has been created.  The dentry pointer representing that
 *		directory is provided as an argument.  Called with
 *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
 *
 *
 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
 * implementations to split any work between atomic (enable) and sleepable
 * (prepare) contexts.  If enabling a clock requires code that might sleep,
 * this must be done in clk_prepare.  Clock enable code that will never be
 * called in a sleepable context may be implemented in clk_enable.
 *
 * Typically, drivers will call clk_prepare when a clock may be needed later
 * (eg. when a device is opened), and clk_enable when the clock is actually
 * required (eg. from an interrupt). Note that clk_prepare MUST have been
 * called before clk_enable.
 */
struct clk_ops {
	int		(*prepare)(struct clk_hw *hw);
	void		(*unprepare)(struct clk_hw *hw);
	int		(*is_prepared)(struct clk_hw *hw);
	void		(*unprepare_unused)(struct clk_hw *hw);
	int		(*enable)(struct clk_hw *hw);
	void		(*disable)(struct clk_hw *hw);
	int		(*is_enabled)(struct clk_hw *hw);
	void		(*disable_unused)(struct clk_hw *hw);
	int		(*save_context)(struct clk_hw *hw);
	void		(*restore_context)(struct clk_hw *hw);
	unsigned long	(*recalc_rate)(struct clk_hw *hw,
					unsigned long parent_rate);
	long		(*round_rate)(struct clk_hw *hw, unsigned long rate,
					unsigned long *parent_rate);
	int		(*determine_rate)(struct clk_hw *hw,
					  struct clk_rate_request *req);
	int		(*set_parent)(struct clk_hw *hw, u8 index);
	u8		(*get_parent)(struct clk_hw *hw);
	int		(*set_rate)(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate);
	int		(*set_rate_and_parent)(struct clk_hw *hw,
				    unsigned long rate,
				    unsigned long parent_rate, u8 index);
	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,
					   unsigned long parent_accuracy);
	int		(*get_phase)(struct clk_hw *hw);
	int		(*set_phase)(struct clk_hw *hw, int degrees);
	int		(*get_duty_cycle)(struct clk_hw *hw,
					  struct clk_duty *duty);
	int		(*set_duty_cycle)(struct clk_hw *hw,
					  struct clk_duty *duty);
	int		(*init)(struct clk_hw *hw);
	void		(*terminate)(struct clk_hw *hw);
	void		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);
};

/**
 * struct clk_parent_data - clk parent information
 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
 * @fw_name: parent name local to provider registering clk
 * @name: globally unique parent name (used as a fallback)
 * @index: parent index local to provider registering clk (if @fw_name absent)
 */
struct clk_parent_data {
	const struct clk_hw	*hw;
	const char		*fw_name;
	const char		*name;
	int			index;
};

/**
 * struct clk_init_data - holds init data that's common to all clocks and is
 * shared between the clock provider and the common clock framework.
 *
 * @name: clock name
 * @ops: operations this clock supports
 * @parent_names: array of string names for all possible parents
 * @parent_data: array of parent data for all possible parents (when some
 *               parents are external to the clk controller)
 * @parent_hws: array of pointers to all possible parents (when all parents
 *              are internal to the clk controller)
 * @num_parents: number of possible parents
 * @flags: framework-level hints and quirks
 */
struct clk_init_data {
	const char		*name;
	const struct clk_ops	*ops;
	/* Only one of the following three should be assigned */
	const char		* const *parent_names;
	const struct clk_parent_data	*parent_data;
	const struct clk_hw		**parent_hws;
	u8			num_parents;
	unsigned long		flags;
};

/**
 * struct clk_hw - handle for traversing from a struct clk to its corresponding
 * hardware-specific structure.  struct clk_hw should be declared within struct
 * clk_foo and then referenced by the struct clk instance that uses struct
 * clk_foo's clk_ops
 *
 * @core: pointer to the struct clk_core instance that points back to this
 * struct clk_hw instance
 *
 * @clk: pointer to the per-user struct clk instance that can be used to call
 * into the clk API
 *
 * @init: pointer to struct clk_init_data that contains the init data shared
 * with the common clock framework. This pointer will be set to NULL once
 * a clk_register() variant is called on this clk_hw pointer.
 */
struct clk_hw {
	struct clk_core *core;
	struct clk *clk;
	const struct clk_init_data *init;
};

/*
 * DOC: Basic clock implementations common to many platforms
 *
 * Each basic clock hardware type is comprised of a structure describing the
 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
 * unique flags for that hardware type, a registration function and an
 * alternative macro for static initialization
 */

/**
 * struct clk_fixed_rate - fixed-rate clock
 * @hw:		handle between common and hardware-specific interfaces
 * @fixed_rate:	constant frequency of clock
 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
 * @flags:	hardware specific flags
 *
 * Flags:
 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
 *                                    instead of what's set in @fixed_accuracy.
 */
struct clk_fixed_rate {
	struct		clk_hw hw;
	unsigned long	fixed_rate;
	unsigned long	fixed_accuracy;
	unsigned long	flags;
};

#define CLK_FIXED_RATE_PARENT_ACCURACY	BIT(0)

extern const struct clk_ops clk_fixed_rate_ops;
struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data, unsigned long flags,
		unsigned long fixed_rate, unsigned long fixed_accuracy,
		unsigned long clk_fixed_flags, bool devm);
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		unsigned long fixed_rate);
/**
 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
 * framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 */
#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate)  \
	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
				     NULL, (flags), (fixed_rate), 0, 0, false)

/**
 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
 * framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 */
#define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate)  \
	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
				     NULL, (flags), (fixed_rate), 0, 0, true)
/**
 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
 * the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_hw: pointer to parent clk
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 */
#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags,     \
					     fixed_rate)		      \
	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw),  \
				     NULL, (flags), (fixed_rate), 0, 0, false)
/**
 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
 * the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_data: parent clk data
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 */
#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags,   \
					     fixed_rate)		      \
	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \
				     (parent_data), (flags), (fixed_rate), 0, \
				     0, false)
/**
 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
 * the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 * @fixed_accuracy: non-adjustable clock accuracy
 */
#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,      \
						 flags, fixed_rate,	      \
						 fixed_accuracy)	      \
	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name),      \
				     NULL, NULL, (flags), (fixed_rate),       \
				     (fixed_accuracy), 0, false)
/**
 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
 * clock with the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_hw: pointer to parent clk
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 * @fixed_accuracy: non-adjustable clock accuracy
 */
#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name,	      \
		parent_hw, flags, fixed_rate, fixed_accuracy)		      \
	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw),  \
				     NULL, (flags), (fixed_rate),	      \
				     (fixed_accuracy), 0, false)
/**
 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
 * clock with the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_data: name of clock's parent
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 * @fixed_accuracy: non-adjustable clock accuracy
 */
#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name,	      \
		parent_data, flags, fixed_rate, fixed_accuracy)		      \
	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \
				     (parent_data), NULL, (flags),	      \
				     (fixed_rate), (fixed_accuracy), 0, false)
/**
 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
 * the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_data: name of clock's parent
 * @flags: framework-specific flags
 * @fixed_rate: non-adjustable clock rate
 */
#define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data,    \
						   flags, fixed_rate)	      \
	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,      \
				     (parent_data), (flags), (fixed_rate), 0,    \
				     CLK_FIXED_RATE_PARENT_ACCURACY, false)

void clk_unregister_fixed_rate(struct clk *clk);
void clk_hw_unregister_fixed_rate(struct clk_hw *hw);

void of_fixed_clk_setup(struct device_node *np);

/**
 * struct clk_gate - gating clock
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @reg:	register controlling gate
 * @bit_idx:	single bit controlling gate
 * @flags:	hardware-specific flags
 * @lock:	register lock
 *
 * Clock which can gate its output.  Implements .enable & .disable
 *
 * Flags:
 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
 *	enable the clock.  Setting this flag does the opposite: setting the bit
 *	disable the clock and clearing it enables the clock
 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
 *	of this register, and mask of gate bits are in higher 16-bit of this
 *	register.  While setting the gate bits, higher 16-bit should also be
 *	updated to indicate changing gate bits.
 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
 *	the gate register.  Setting this flag makes the register accesses big
 *	endian.
 */
struct clk_gate {
	struct clk_hw hw;
	void __iomem	*reg;
	u8		bit_idx;
	u8		flags;
	spinlock_t	*lock;
};

#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)

#define CLK_GATE_SET_TO_DISABLE		BIT(0)
#define CLK_GATE_HIWORD_MASK		BIT(1)
#define CLK_GATE_BIG_ENDIAN		BIT(2)

extern const struct clk_ops clk_gate_ops;
struct clk_hw *__clk_hw_register_gate(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data,
		unsigned long flags,
		void __iomem *reg, u8 bit_idx,
		u8 clk_gate_flags, spinlock_t *lock);
struct clk *clk_register_gate(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 bit_idx,
		u8 clk_gate_flags, spinlock_t *lock);
/**
 * clk_hw_register_gate - register a gate clock with the clock framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_name: name of this clock's parent
 * @flags: framework-specific flags for this clock
 * @reg: register address to control gating of this clock
 * @bit_idx: which bit in the register controls gating of this clock
 * @clk_gate_flags: gate-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \
			     clk_gate_flags, lock)			      \
	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
			       NULL, (flags), (reg), (bit_idx),		      \
			       (clk_gate_flags), (lock))
/**
 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
 * framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_hw: pointer to parent clk
 * @flags: framework-specific flags for this clock
 * @reg: register address to control gating of this clock
 * @bit_idx: which bit in the register controls gating of this clock
 * @clk_gate_flags: gate-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \
				       bit_idx, clk_gate_flags, lock)	      \
	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
			       NULL, (flags), (reg), (bit_idx),		      \
			       (clk_gate_flags), (lock))
/**
 * clk_hw_register_gate_parent_data - register a gate clock with the clock
 * framework
 * @dev: device that is registering this clock
 * @name: name of this clock
 * @parent_data: parent clk data
 * @flags: framework-specific flags for this clock
 * @reg: register address to control gating of this clock
 * @bit_idx: which bit in the register controls gating of this clock
 * @clk_gate_flags: gate-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \
				       bit_idx, clk_gate_flags, lock)	      \
	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
			       (flags), (reg), (bit_idx),		      \
			       (clk_gate_flags), (lock))
void clk_unregister_gate(struct clk *clk);
void clk_hw_unregister_gate(struct clk_hw *hw);
int clk_gate_is_enabled(struct clk_hw *hw);

struct clk_div_table {
	unsigned int	val;
	unsigned int	div;
};

/**
 * struct clk_divider - adjustable divider clock
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @reg:	register containing the divider
 * @shift:	shift to the divider bit field
 * @width:	width of the divider bit field
 * @table:	array of value/divider pairs, last entry should have div = 0
 * @lock:	register lock
 *
 * Clock with an adjustable divider affecting its output frequency.  Implements
 * .recalc_rate, .set_rate and .round_rate
 *
 * @flags:
 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
 *	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
 *	the raw value read from the register, with the value of zero considered
 *	invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
 *	the hardware register
 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
 *	CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
 *	Some hardware implementations gracefully handle this case and allow a
 *	zero divisor by not modifying their input clock
 *	(divide by one / bypass).
 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
 *	of this register, and mask of divider bits are in higher 16-bit of this
 *	register.  While setting the divider bits, higher 16-bit should also be
 *	updated to indicate changing divider bits.
 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
 *	to the closest integer instead of the up one.
 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
 *	not be changed by the clock framework.
 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
 *	except when the value read from the register is zero, the divisor is
 *	2^width of the field.
 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
 *	for the divider register.  Setting this flag makes the register accesses
 *	big endian.
 */
struct clk_divider {
	struct clk_hw	hw;
	void __iomem	*reg;
	u8		shift;
	u8		width;
	u8		flags;
	const struct clk_div_table	*table;
	spinlock_t	*lock;
};

#define clk_div_mask(width)	((1 << (width)) - 1)
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)

#define CLK_DIVIDER_ONE_BASED		BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
#define CLK_DIVIDER_HIWORD_MASK		BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
#define CLK_DIVIDER_READ_ONLY		BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
#define CLK_DIVIDER_BIG_ENDIAN		BIT(7)

extern const struct clk_ops clk_divider_ops;
extern const struct clk_ops clk_divider_ro_ops;

unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
		unsigned int val, const struct clk_div_table *table,
		unsigned long flags, unsigned long width);
long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
			       unsigned long rate, unsigned long *prate,
			       const struct clk_div_table *table,
			       u8 width, unsigned long flags);
long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
				  unsigned long rate, unsigned long *prate,
				  const struct clk_div_table *table, u8 width,
				  unsigned long flags, unsigned int val);
int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
			   const struct clk_div_table *table, u8 width,
			   unsigned long flags);
int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
			      const struct clk_div_table *table, u8 width,
			      unsigned long flags, unsigned int val);
int divider_get_val(unsigned long rate, unsigned long parent_rate,
		const struct clk_div_table *table, u8 width,
		unsigned long flags);

struct clk_hw *__clk_hw_register_divider(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
		const struct clk_div_table *table, spinlock_t *lock);
struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
		const struct clk_div_table *table, spinlock_t *lock);
struct clk *clk_register_divider_table(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock);
/**
 * clk_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
			     clk_divider_flags, lock)			       \
	clk_register_divider_table((dev), (name), (parent_name), (flags),      \
				   (reg), (shift), (width),		       \
				   (clk_divider_flags), NULL, (lock))
/**
 * clk_hw_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \
				width, clk_divider_flags, lock)		      \
	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
				  NULL, (flags), (reg), (shift), (width),     \
				  (clk_divider_flags), NULL, (lock))
/**
 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
 * framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_hw: pointer to parent clk
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg,   \
					  shift, width, clk_divider_flags,    \
					  lock)				      \
	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
				  NULL, (flags), (reg), (shift), (width),     \
				  (clk_divider_flags), NULL, (lock))
/**
 * clk_hw_register_divider_parent_data - register a divider clock with the clock
 * framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_data: parent clk data
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags,    \
					    reg, shift, width,		      \
					    clk_divider_flags, lock)	      \
	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \
				  (parent_data), (flags), (reg), (shift),     \
				  (width), (clk_divider_flags), NULL, (lock))
/**
 * clk_hw_register_divider_table - register a table based divider clock with
 * the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg,     \
				      shift, width, clk_divider_flags, table, \
				      lock)				      \
	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
				  NULL, (flags), (reg), (shift), (width),     \
				  (clk_divider_flags), (table), (lock))
/**
 * clk_hw_register_divider_table_parent_hw - register a table based divider
 * clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_hw: pointer to parent clk
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags,  \
						reg, shift, width,	      \
						clk_divider_flags, table,     \
						lock)			      \
	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
				  NULL, (flags), (reg), (shift), (width),     \
				  (clk_divider_flags), (table), (lock))
/**
 * clk_hw_register_divider_table_parent_data - register a table based divider
 * clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_data: parent clk data
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
#define clk_hw_register_divider_table_parent_data(dev, name, parent_data,     \
						  flags, reg, shift, width,   \
						  clk_divider_flags, table,   \
						  lock)			      \
	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \
				  (parent_data), (flags), (reg), (shift),     \
				  (width), (clk_divider_flags), (table),      \
				  (lock))
/**
 * devm_clk_hw_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \
				width, clk_divider_flags, lock)		      \
	__devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
				  NULL, (flags), (reg), (shift), (width),     \
				  (clk_divider_flags), NULL, (lock))
/**
 * devm_clk_hw_register_divider_table - register a table based divider clock
 * with the clock framework (devres variant)
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags,     \
					   reg, shift, width,		      \
					   clk_divider_flags, table, lock)    \
	__devm_clk_hw_register_divider((dev), NULL, (name), (parent_name),    \
				       NULL, NULL, (flags), (reg), (shift),   \
				       (width), (clk_divider_flags), (table), \
				       (lock))

void clk_unregister_divider(struct clk *clk);
void clk_hw_unregister_divider(struct clk_hw *hw);

/**
 * struct clk_mux - multiplexer clock
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @reg:	register controlling multiplexer
 * @table:	array of register values corresponding to the parent index
 * @shift:	shift to multiplexer bit field
 * @mask:	mask of mutliplexer bit field
 * @flags:	hardware-specific flags
 * @lock:	register lock
 *
 * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
 * and .recalc_rate
 *
 * Flags:
 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
 *	register, and mask of mux bits are in higher 16-bit of this register.
 *	While setting the mux bits, higher 16-bit should also be updated to
 *	indicate changing mux bits.
 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
 * 	.get_parent clk_op.
 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
 *	frequency.
 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
 *	the mux register.  Setting this flag makes the register accesses big
 *	endian.
 */
struct clk_mux {
	struct clk_hw	hw;
	void __iomem	*reg;
	u32		*table;
	u32		mask;
	u8		shift;
	u8		flags;
	spinlock_t	*lock;
};

#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)

#define CLK_MUX_INDEX_ONE		BIT(0)
#define CLK_MUX_INDEX_BIT		BIT(1)
#define CLK_MUX_HIWORD_MASK		BIT(2)
#define CLK_MUX_READ_ONLY		BIT(3) /* mux can't be changed */
#define CLK_MUX_ROUND_CLOSEST		BIT(4)
#define CLK_MUX_BIG_ENDIAN		BIT(5)

extern const struct clk_ops clk_mux_ops;
extern const struct clk_ops clk_mux_ro_ops;

struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
		const char *name, u8 num_parents,
		const char * const *parent_names,
		const struct clk_hw **parent_hws,
		const struct clk_parent_data *parent_data,
		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
		const char *name, u8 num_parents,
		const char * const *parent_names,
		const struct clk_hw **parent_hws,
		const struct clk_parent_data *parent_data,
		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
struct clk *clk_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock);

#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg,    \
			 shift, width, clk_mux_flags, lock)		      \
	clk_register_mux_table((dev), (name), (parent_names), (num_parents),  \
			       (flags), (reg), (shift), BIT((width)) - 1,     \
			       (clk_mux_flags), NULL, (lock))
#define clk_hw_register_mux_table(dev, name, parent_names, num_parents,	      \
				  flags, reg, shift, mask, clk_mux_flags,     \
				  table, lock)				      \
	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
			      (parent_names), NULL, NULL, (flags), (reg),     \
			      (shift), (mask), (clk_mux_flags), (table),      \
			      (lock))
#define clk_hw_register_mux_table_parent_data(dev, name, parent_data,	      \
				  num_parents, flags, reg, shift, mask,	      \
				  clk_mux_flags, table, lock)		      \
	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
			      NULL, NULL, (parent_data), (flags), (reg),      \
			      (shift), (mask), (clk_mux_flags), (table),      \
			      (lock))
#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
			    shift, width, clk_mux_flags, lock)		      \
	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
			      (parent_names), NULL, NULL, (flags), (reg),     \
			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
			      NULL, (lock))
#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags,    \
				reg, shift, width, clk_mux_flags, lock)	      \
	__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL,	      \
			      (parent_hws), NULL, (flags), (reg), (shift),    \
			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents,  \
					flags, reg, shift, width,	      \
					clk_mux_flags, lock)		      \
	__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
			      (parent_data), (flags), (reg), (shift),	      \
			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
			    shift, width, clk_mux_flags, lock)		      \
	__devm_clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
			      (parent_names), NULL, NULL, (flags), (reg),     \
			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
			      NULL, (lock))

int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
			 unsigned int val);
unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);

void clk_unregister_mux(struct clk *clk);
void clk_hw_unregister_mux(struct clk_hw *hw);

void of_fixed_factor_clk_setup(struct device_node *node);

/**
 * struct clk_fixed_factor - fixed multiplier and divider clock
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @mult:	multiplier
 * @div:	divider
 *
 * Clock with a fixed multiplier and divider. The output frequency is the
 * parent clock rate divided by div and multiplied by mult.
 * Implements .recalc_rate, .set_rate and .round_rate
 */

struct clk_fixed_factor {
	struct clk_hw	hw;
	unsigned int	mult;
	unsigned int	div;
};

#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)

extern const struct clk_ops clk_fixed_factor_ops;
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		unsigned int mult, unsigned int div);
void clk_unregister_fixed_factor(struct clk *clk);
struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		unsigned int mult, unsigned int div);
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		unsigned int mult, unsigned int div);
/**
 * struct clk_fractional_divider - adjustable fractional divider clock
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @reg:	register containing the divider
 * @mshift:	shift to the numerator bit field
 * @mwidth:	width of the numerator bit field
 * @nshift:	shift to the denominator bit field
 * @nwidth:	width of the denominator bit field
 * @approximation: clk driver's callback for calculating the divider clock
 * @lock:	register lock
 *
 * Clock with adjustable fractional divider affecting its output frequency.
 *
 * @flags:
 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
 *	is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
 *	is set then the numerator and denominator are both the value read
 *	plus one.
 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
 *	used for the divider register.  Setting this flag makes the register
 *	accesses big endian.
 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
 *	be saturated and the caller will get quite far from the good enough
 *	approximation. Instead the caller may require, by setting this flag,
 *	to shift left by a few bits in case, when the asked one is quite small
 *	to satisfy the desired range of denominator. It assumes that on the
 *	caller's side the power-of-two capable prescaler exists.
 */
struct clk_fractional_divider {
	struct clk_hw	hw;
	void __iomem	*reg;
	u8		mshift;
	u8		mwidth;
	u32		mmask;
	u8		nshift;
	u8		nwidth;
	u32		nmask;
	u8		flags;
	void		(*approximation)(struct clk_hw *hw,
				unsigned long rate, unsigned long *parent_rate,
				unsigned long *m, unsigned long *n);
	spinlock_t	*lock;
};

#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)

#define CLK_FRAC_DIVIDER_ZERO_BASED		BIT(0)
#define CLK_FRAC_DIVIDER_BIG_ENDIAN		BIT(1)
#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS	BIT(2)

struct clk *clk_register_fractional_divider(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
		u8 clk_divider_flags, spinlock_t *lock);
struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
		u8 clk_divider_flags, spinlock_t *lock);
void clk_hw_unregister_fractional_divider(struct clk_hw *hw);

/**
 * struct clk_multiplier - adjustable multiplier clock
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @reg:	register containing the multiplier
 * @shift:	shift to the multiplier bit field
 * @width:	width of the multiplier bit field
 * @lock:	register lock
 *
 * Clock with an adjustable multiplier affecting its output frequency.
 * Implements .recalc_rate, .set_rate and .round_rate
 *
 * @flags:
 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
 *	from the register, with 0 being a valid value effectively
 *	zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
 *	set, then a null multiplier will be considered as a bypass,
 *	leaving the parent rate unmodified.
 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
 *	rounded to the closest integer instead of the down one.
 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
 *	used for the multiplier register.  Setting this flag makes the register
 *	accesses big endian.
 */
struct clk_multiplier {
	struct clk_hw	hw;
	void __iomem	*reg;
	u8		shift;
	u8		width;
	u8		flags;
	spinlock_t	*lock;
};

#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)

#define CLK_MULTIPLIER_ZERO_BYPASS	BIT(0)
#define CLK_MULTIPLIER_ROUND_CLOSEST	BIT(1)
#define CLK_MULTIPLIER_BIG_ENDIAN	BIT(2)

extern const struct clk_ops clk_multiplier_ops;

/***
 * struct clk_composite - aggregate clock of mux, divider and gate clocks
 *
 * @hw:		handle between common and hardware-specific interfaces
 * @mux_hw:	handle between composite and hardware-specific mux clock
 * @rate_hw:	handle between composite and hardware-specific rate clock
 * @gate_hw:	handle between composite and hardware-specific gate clock
 * @mux_ops:	clock ops for mux
 * @rate_ops:	clock ops for rate
 * @gate_ops:	clock ops for gate
 */
struct clk_composite {
	struct clk_hw	hw;
	struct clk_ops	ops;

struct clk_hw	*mux_hw;
	struct clk_hw	*rate_hw;
	struct clk_hw	*gate_hw;

const struct clk_ops	*mux_ops;
	const struct clk_ops	*rate_ops;
	const struct clk_ops	*gate_ops;
};

#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)

struct clk *clk_register_composite(struct device *dev, const char *name,
		const char * const *parent_names, int num_parents,
		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
		unsigned long flags);
struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
		const struct clk_parent_data *parent_data, int num_parents,
		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
		unsigned long flags);
void clk_unregister_composite(struct clk *clk);
struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
		const char * const *parent_names, int num_parents,
		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
		unsigned long flags);
struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
		const char *name,
		const struct clk_parent_data *parent_data, int num_parents,
		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
		unsigned long flags);
struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
		const char *name, const struct clk_parent_data *parent_data,
		int num_parents,
		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
		unsigned long flags);
void clk_hw_unregister_composite(struct clk_hw *hw);

struct clk *clk_register(struct device *dev, struct clk_hw *hw);
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);

int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);

void clk_unregister(struct clk *clk);
void devm_clk_unregister(struct device *dev, struct clk *clk);

void clk_hw_unregister(struct clk_hw *hw);
void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);

/* helper functions */
const char *__clk_get_name(const struct clk *clk);
const char *clk_hw_get_name(const struct clk_hw *hw);
#ifdef CONFIG_COMMON_CLK
struct clk_hw *__clk_get_hw(struct clk *clk);
#else
static inline struct clk_hw *__clk_get_hw(struct clk *clk)
{
	return (struct clk_hw *)clk;
}
#endif

struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
				const char *con_id);

unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
					  unsigned int index);
int clk_hw_get_parent_index(struct clk_hw *hw);
int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
unsigned int __clk_get_enable_count(struct clk *clk);
unsigned long clk_hw_get_rate(const struct clk_hw *hw);
unsigned long clk_hw_get_flags(const struct clk_hw *hw);
#define clk_hw_can_set_rate_parent(hw) \
	(clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)

bool clk_hw_is_prepared(const struct clk_hw *hw);
bool clk_hw_rate_is_protected(const struct clk_hw *hw);
bool clk_hw_is_enabled(const struct clk_hw *hw);
bool __clk_is_enabled(struct clk *clk);
struct clk *__clk_lookup(const char *name);
int __clk_mux_determine_rate(struct clk_hw *hw,
			     struct clk_rate_request *req);
int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
int __clk_mux_determine_rate_closest(struct clk_hw *hw,
				     struct clk_rate_request *req);
int clk_mux_determine_rate_flags(struct clk_hw *hw,
				 struct clk_rate_request *req,
				 unsigned long flags);
void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
			   unsigned long max_rate);

static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
{
	dst->clk = src->clk;
	dst->core = src->core;
}

static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long *prate,
				      const struct clk_div_table *table,
				      u8 width, unsigned long flags)
{
	return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
					 rate, prate, table, width, flags);
}

static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
					 unsigned long *prate,
					 const struct clk_div_table *table,
					 u8 width, unsigned long flags,
					 unsigned int val)
{
	return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
					    rate, prate, table, width, flags,
					    val);
}

/*
 * FIXME clock api without lock protection
 */
unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);

struct clk_onecell_data {
	struct clk **clks;
	unsigned int clk_num;
};

struct clk_hw_onecell_data {
	unsigned int num;
	struct clk_hw *hws[];
};

#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)

/*
 * Use this macro when you have a driver that requires two initialization
 * routines, one at of_clk_init(), and one at platform device probe
 */
#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
	static void __init name##_of_clk_init_driver(struct device_node *np) \
	{								\
		of_node_clear_flag(np, OF_POPULATED);			\
		fn(np);							\
	}								\
	OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)

#define CLK_HW_INIT(_name, _parent, _ops, _flags)		\
	(&(struct clk_init_data) {				\
		.flags		= _flags,			\
		.name		= _name,			\
		.parent_names	= (const char *[]) { _parent },	\
		.num_parents	= 1,				\
		.ops		= _ops,				\
	})

#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags)			\
	(&(struct clk_init_data) {					\
		.flags		= _flags,				\
		.name		= _name,				\
		.parent_hws	= (const struct clk_hw*[]) { _parent },	\
		.num_parents	= 1,					\
		.ops		= _ops,					\
	})

/*
 * This macro is intended for drivers to be able to share the otherwise
 * individual struct clk_hw[] compound literals created by the compiler
 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
 */
#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags)			\
	(&(struct clk_init_data) {					\
		.flags		= _flags,				\
		.name		= _name,				\
		.parent_hws	= _parent,				\
		.num_parents	= 1,					\
		.ops		= _ops,					\
	})

#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags)		\
	(&(struct clk_init_data) {					\
		.flags		= _flags,				\
		.name		= _name,				\
		.parent_data	= (const struct clk_parent_data[]) {	\
					{ .fw_name = _parent },		\
				  },					\
		.num_parents	= 1,					\
		.ops		= _ops,					\
	})

#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags)	\
	(&(struct clk_init_data) {				\
		.flags		= _flags,			\
		.name		= _name,			\
		.parent_names	= _parents,			\
		.num_parents	= ARRAY_SIZE(_parents),		\
		.ops		= _ops,				\
	})

#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags)	\
	(&(struct clk_init_data) {				\
		.flags		= _flags,			\
		.name		= _name,			\
		.parent_hws	= _parents,			\
		.num_parents	= ARRAY_SIZE(_parents),		\
		.ops		= _ops,				\
	})

#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags)	\
	(&(struct clk_init_data) {				\
		.flags		= _flags,			\
		.name		= _name,			\
		.parent_data	= _parents,			\
		.num_parents	= ARRAY_SIZE(_parents),		\
		.ops		= _ops,				\
	})

#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags)	\
	(&(struct clk_init_data) {			\
		.flags          = _flags,		\
		.name           = _name,		\
		.parent_names   = NULL,			\
		.num_parents    = 0,			\
		.ops            = _ops,			\
	})

#define CLK_FIXED_FACTOR(_struct, _name, _parent,			\
			_div, _mult, _flags)				\
	struct clk_fixed_factor _struct = {				\
		.div		= _div,					\
		.mult		= _mult,				\
		.hw.init	= CLK_HW_INIT(_name,			\
					      _parent,			\
					      &clk_fixed_factor_ops,	\
					      _flags),			\
	}

#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent,			\
			    _div, _mult, _flags)			\
	struct clk_fixed_factor _struct = {				\
		.div		= _div,					\
		.mult		= _mult,				\
		.hw.init	= CLK_HW_INIT_HW(_name,			\
						 _parent,		\
						 &clk_fixed_factor_ops,	\
						 _flags),		\
	}

/*
 * This macro allows the driver to reuse the _parent array for multiple
 * fixed factor clk declarations.
 */
#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent,			\
			     _div, _mult, _flags)			\
	struct clk_fixed_factor _struct = {				\
		.div		= _div,					\
		.mult		= _mult,				\
		.hw.init	= CLK_HW_INIT_HWS(_name,		\
						  _parent,		\
						  &clk_fixed_factor_ops, \
						  _flags),	\
	}

#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent,		\
				 _div, _mult, _flags)			\
	struct clk_fixed_factor _struct = {				\
		.div		= _div,					\
		.mult		= _mult,				\
		.hw.init	= CLK_HW_INIT_FW_NAME(_name,		\
						      _parent,		\
						      &clk_fixed_factor_ops, \
						      _flags),		\
	}

#ifdef CONFIG_OF
int of_clk_add_provider(struct device_node *np,
			struct clk *(*clk_src_get)(struct of_phandle_args *args,
						   void *data),
			void *data);
int of_clk_add_hw_provider(struct device_node *np,
			   struct clk_hw *(*get)(struct of_phandle_args *clkspec,
						 void *data),
			   void *data);
int devm_of_clk_add_hw_provider(struct device *dev,
			   struct clk_hw *(*get)(struct of_phandle_args *clkspec,
						 void *data),
			   void *data);
void of_clk_del_provider(struct device_node *np);
void devm_of_clk_del_provider(struct device *dev);
struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
				  void *data);
struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
				    void *data);
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
				     void *data);
int of_clk_parent_fill(struct device_node *np, const char **parents,
		       unsigned int size);
int of_clk_detect_critical(struct device_node *np, int index,
			    unsigned long *flags);

#else /* !CONFIG_OF */

static inline int of_clk_add_provider(struct device_node *np,
			struct clk *(*clk_src_get)(struct of_phandle_args *args,
						   void *data),
			void *data)
{
	return 0;
}
static inline int of_clk_add_hw_provider(struct device_node *np,
			struct clk_hw *(*get)(struct of_phandle_args *clkspec,
					      void *data),
			void *data)
{
	return 0;
}
static inline int devm_of_clk_add_hw_provider(struct device *dev,
			   struct clk_hw *(*get)(struct of_phandle_args *clkspec,
						 void *data),
			   void *data)
{
	return 0;
}
static inline void of_clk_del_provider(struct device_node *np) {}
static inline void devm_of_clk_del_provider(struct device *dev) {}
static inline struct clk *of_clk_src_simple_get(
	struct of_phandle_args *clkspec, void *data)
{
	return ERR_PTR(-ENOENT);
}
static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
{
	return ERR_PTR(-ENOENT);
}
static inline struct clk *of_clk_src_onecell_get(
	struct of_phandle_args *clkspec, void *data)
{
	return ERR_PTR(-ENOENT);
}
static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
{
	return ERR_PTR(-ENOENT);
}
static inline int of_clk_parent_fill(struct device_node *np,
				     const char **parents, unsigned int size)
{
	return 0;
}
static inline int of_clk_detect_critical(struct device_node *np, int index,
					  unsigned long *flags)
{
	return 0;
}
#endif /* CONFIG_OF */

void clk_gate_restore_context(struct clk_hw *hw);

#endif /* CLK_PROVIDER_H */